Layout Engineer

Headway Tek Inc; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Headway Tek Inc in Bengaluru is seeking a memory layout engineer to work on advanced memory architectures and layouts at submicron nodes. You will contribute to memory stack design and ensure physical closure while collaborating with cross-functional teams to optimize density and performance.

The ideal candidate has a degree in Electrical Engineering and hands-on experience with SRAM/DRAM, memory IPs, and Cadence/Synopsys tools for layout and verification, plus FinFET rules and DFM knowledge.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering required.
• Experience with memory layouts and sub-micron design practices.
• Proficiency with DRC/LVS and memory verification.
• Knowledge of FinFET rules and memory architecture.
• Experience with Cadence/Synopsys for layout and verification; Mentor tools for integration.

Responsibilities

• Design and optimize memory block layouts including bitcells, decoders, and I/O blocks.
• Ensure DRC/LVS density verification and physical closure.
• Address IR/EM challenges in memory layouts.
• Collaborate with circuit, PDK, and methodology teams.

Skills

Memory layout design

SRAM/DRAM memory

Memory compiler IPs

Top-level memory integration

DFM guidelines

IR/EM challenges

Layout optimization

FinFET design rules

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Cadence tools

Synopsys tools

Mentor Graphics tools

Job description

Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes

Qualifications: Bachelor's or Master's degree in Electrical Engineering.

Key Skills & Responsibilities:

• Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc.
• Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits
• Expertise in top-level memory integration, DRC, LVS, density verification, and physical closure
• Understanding of IR/EM challenges in memory layouts
• Proficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verification
• Exposure to ultra-deep sub-micron design challenges and DFM guidelines
• Knowledge of memory architecture, bitcell layout concepts, and FinFET design rules
• Ability to optimize layout for area, power, speed, yield, and manufacturability
• Collaboration with circuit design, verification, PDK, and methodology teams