Senior ASIC RTL Engineer, Integration

Google; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading technology company is seeking a Senior ASIC RTL Engineer in Bengaluru, Karnataka, to develop custom silicon solutions. Candidates should have at least 8 years of experience with digital logic design and RTL principles using Verilog or SystemVerilog, as well as automation scripting skills. The role includes collaborating with cross-functional teams and involves both design and integration tasks, contributing to innovative hardware experiences cherished by millions globally.

Qualifications

• 8 years of experience with digital logic design and RTL design.
• Experience with low-power design techniques and logic synthesis.
• Integration and automation of flows for sub-systems.

Responsibilities

• Work with RTL engineers on IP/Subsystem development and automation.
• Interact with architecture team to meet quality and design goals.
• Collaborate with cross-functional teams on design decisions.

Skills

Digital logic design principles

RTL design concepts

Verilog

SystemVerilog

Automation scripting languages (Perl, Python, TCL)

Logic synthesis techniques

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

Senior ASIC RTL Engineer, Integration – Google

Location: Bengaluru, Karnataka buit?

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide, shaping next‑generation hardware experiences for unparalleled performance, efficiency, and integration deze.

The Platforms and Devices team encompasses Google’s various computing software platforms across environments (desktop, mobile, applications), as well as our first‑party devices and services that combine AI, software, and hardware. Teams across this area research, design, and develop new technologies to make users’ interactions with computing faster and more seamless.

Responsibilities

• Work with a team of RTL engineers with IP/Subsystem development to plan tasks, build subsystems, run quality flows, create automation, and hold code and design reviews.
_ACTOR: code development of complex features in the IP/Subsystem.
• Interact closely with the architecture team to develop implementation (microarchitecture and coding) strategies meeting quality, schedule and PPA for the IP.
• Collaborate with the cross‑functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with automation scripting languages such as Perl, Python, TCL.
• Experience with logic synthesis techniques to optimize area, performance and power, as well as low‑power design techniques.
• Experience integrating, designing and automating flows of sub‑systems, interconnects (AXI 4/5, ACE‑Lite, AHB, APB) and other component IPs.

Preferred Qualifications

• Master’s or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• 12 years of experience with digital logic design principles and RTL design concepts using Verilog or SystemVerilog.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high‑performance and low‑power design techniques, assertion‑based formal verification, FPGA and emulation platforms, and SOC architecture.
• živnow and memoization of memory compression, fabric, coherence, cache, or DRAM.

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

Job Function

• Other, Information Technology, and Engineering

Industries

• Information Services and Technology, Information and Internet

EEO Statement

Google is proud to be an equal‑opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation literacy , age, citizenship, marital status or disability. We also consider qualified web designer regardless nipa criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need require accommodation, please let us know by completing our Accommodations for Applicants form.