Senior ASIC RTL Design Engineer

Google India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Google India Pvt Ltd. is seeking a Senior ASIC RTL Engineer to drive RTL coding and verification across advanced Fabrics and Network-on-Chip subsystems.

You will contribute to the design and validation from concept to tape-out, delivering high-performance, power-efficient silicon for Google's hardware platform. The role requires hands-on expertise in Verilog/SystemVerilog, logic synthesis, and low-power techniques, with experience in ASIC/FPGA verification and DFT.

Qualifications

• Bachelor's degree or equivalent practical experience in Electrical/Computer Engineering or related field.
• 8 years of experience with digital logic design, RTL design concepts and Verilog/SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code for performance and power, and low-power design techniques.

Responsibilities

• Perform RTL coding, function/performance simulation, debug, and Lint/CDC/Formal Verification checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Own and execute RTL design and micro-architecture for high-performance Fabrics and NoC subsystems from concept to tape-out.
• Write production-quality SystemVerilog code for complex logic including cache coherency controllers.
• Debug complex silicon issues and architectural bugs by analyzing waveforms and gate-level simulations.

Skills

RTL design principles

Verilog/SystemVerilog

low-power design techniques

logic synthesis techniques

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

ASIC/FPGA design verification

Synthesis

Timing/power analysis

DFT

Lint

CDC

Job description

Senior ASIC RTL Engineer

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• Experience with a scripting language like Perl or Python.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Experience in one or more functional areas, such as coherent fabrics (e.g., AMBA CHI/AXI), memory controllers (e.g., LPDDR5, DDR5), or I/O controllers (e.g., PCIe, CXL).
• Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
• Knowledge of memory compression, fabric, coherence, cache, or DRAM.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out.
• Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers.
• Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations.

Experience Level Senior Level