Senior Silicon Digital Design Engineer, Core IP

Google; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Google is seeking a Senior Silicon Digital Design Engineer to contribute to innovative silicon solutions that power their products. The role includes defining microarchitecture, developing RTL implementations, and collaborating with various teams. With a focus on performance and efficiency, the successful candidate will help shape hardware experiences for users worldwide.

A Bachelor’s degree in a relevant field and 8 years of experience are key qualifications. Join Google in a role that emphasizes cutting-edge technology and teamwork.

Qualifications

• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code and low-power design techniques.
• Knowledge of high-performance design techniques and software design skills.

Responsibilities

• Provide microarchitecture definition for Core IP hardware designs and subsystem integration.
• Define and develop RTL implementations that meet power, performance and area goals.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.

Skills

digital logic design principles

RTL design concepts

Verilog or SystemVerilog

ASIC design methodologies

low-power design techniques

machine learning accelerators

C/C++ programming

high-performance design techniques

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science

Job description

Senior Silicon Digital Design Engineer, Core IP

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low‑power design techniques.
• Experience with ASIC design methodologies for clock domain checks and reset checks.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience implementing machine learning accelerators, camera ISP image processing IP, or other multimedia IPs such as display or video codec.
• Proficient in scripting languages, C/C++ programming and software design skills.
• Knowledge of high‑performance and low‑power design techniques, assertion‑based formal verification, FPGA and emulation platforms, and SOC architecture.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first‑party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our users' interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top‑level integration.
• Define and develop RTL implementations that meet power, performance and area goals.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure and FPGA/silicon bring‑up.
• Work with multi‑disciplined and multi‑site teams in RTL design, verification, or architecture/micro‑architecture planning.

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