ASIC RTL Design Engineer III, Silicon

Google Inc.; Bengaluru; On-site; INR 1,200,000 - 1,500,000; Full time

Job summary

Google Inc. is seeking a skilled hardware engineer to develop custom silicon solutions that enhance user experiences. In this pivotal role, you will shape the architecture of mobile SOC subsystems, ensuring integration and quality across various components and systems. Your efforts will support products that are integral to Google's direct-to-consumer offerings.

A successful candidate should possess both a Bachelor's degree in a related field and at least four years of experience with digital logic design. This position emphasizes collaboration with cross-functional teams, ensuring timely delivery of high-quality designs.

Qualifications

• 4 years of experience with digital logic design principles.
• Experience with logic synthesis techniques for optimizing RTL code.
• Knowledge of ASIC or FPGA design verification and performance analysis.

Responsibilities

• Define block-level design documents including roadmap and protocols.
• Perform RTL coding and simulation debugging.
• Participate in synthesis and timing/power closure.

Skills

Digital logic design principles

RTL design concepts

Verilog or SystemVerilog

Low-power design techniques

Scripting languages (Perl/Python)

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's or PhD in related fields

Job description

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low‑power design techniques.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with a scripting language like Perl or Python.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
• Knowledge of memory compression, fabric, coherence, cache, or DRAM.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role you will help create the micro‑architecture of the mobile SOC's subsystems, integrate multiple first‑party/third‑party components, and run extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will deliver subsystems on time and collaborate with cross‑functional teams (DV/DFT/PD/Power) to ensure quality.

The Platforms and Devices team encompasses Google's computing platforms across desktop, mobile, and application environments, as well as first‑party devices and services that combine the best of Google AI, software, and hardware. Teams in this area research, design, and develop new technologies to make user interactions faster and more seamless, building innovative experiences worldwide.

Responsibilities

• Define the block‑level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
• Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring‑up.
• Participate in test plan and coverage analysis of the block and ASIC‑level verification.
• Communicate and work with multi‑disciplined and multi‑site teams.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.