Micro-architecture and RTL Lead, Google Cloud

Google; Bengaluru; On-site; INR 3,000,000 - 5,400,000; Full time

Job summary

Google is seeking a highly experienced ASIC verification and IP/SoC integration engineer to shape TPU architecture and verify complex digital designs. Based in Bengaluru, you will collaborate with architecture, verification, power and physical design teams to deliver high‑quality data center accelerators.

The role requires 10+ years in ASIC development with Verilog/SystemVerilog and VHDL, plus DFT, timing and power analysis.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
• Experience in micro-architecture and design of IPs and subsystems in networking domain such as packet processing, bandwidth management, congestion control, etc.

Responsibilities

• Drive development of complex IPs and subsystems along with a team of Engineers in the Bengaluru design organization.
• Own microarchitecture and implementation of IPs and subsystems.
• Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
• Identify and drive Power, Performance and Area (PPA) improvements for the domains owned.

Skills

Verilog/SystemVerilog

VHDL

ASIC design verification

Synthesis

DFT

Micro-architecture

IP/Subsystem design

Networking IPs

Timing/Power analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro‑architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
• Experience in micro‑architecture and design of IPs and subsystems in networking domain such as packet processing, bandwidth management, congestion control, etc.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with programming languages (e.g., Python, C/C++ or Perl).
• Experience in SoC designs and integration flows.
• Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.
• Knowledge of high performance and low power design techniques.

Responsibilities

• Drive development of complex IPs and subsystems along with a team of Engineers in the Bengaluru design organization.
• Own microarchitecture and implementation of IPs and subsystems.
• Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
• Identify and drive Power, Performance and Area (PPA) improvements for the domains owned.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.