Senior Silicon Physical Design Engineer, Google Cloud

Google; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Google Cloud seeks a Senior Silicon Physical Design Engineer in Bengaluru to drive physical design for data-center accelerators. You will collaborate across architecture, verification, power, and PD teams to deliver high-performance, power-efficient SoCs for ML workloads.

The role emphasizes innovative micro-architecture and robust timing/power solutions, contributing to Google’s scalable hardware platforms.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience with advanced design including clock/voltage domain crossing, DFT, and low-power designs.
• Experience with SoC cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Skills

Electrical Engineering

DFT

Clock/Voltage Crossing

Low Power Designs

SoC Cycles

High-Performance/High-Frequency Design

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

SystemVerilog

TCL

STA

Job description

Senior Silicon Physical Design Engineer, Google Cloud

Location: Bengaluru, Karnataka, India

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master’s degree in Electrical Engineering.
• Experience in coding with System Verilog and scripting with Tool Command Language (TCL).
• Experience in VLSI design in SoC or experience with multiple‑cycles of SoC in ASIC design.
• Experience in coding constraints and scripting with TCL.
• Experience with Static Timing Analysis (STA) convergence on blocks/Subsystem (SS)/SoC

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing SoCs used to accelerate Machine Learning (ML) computation in data centers. You will collaborate with members of architecture, verification, power and performance, and physical design to specify and deliver high‑quality designs for next‑generation data center accelerators. You will solve technical problems with innovative micro‑architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

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