Senior Principal Physical Design Engineer

MaxLinear; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

MaxLinear is seeking a Senior Principal Physical Design Engineer in Bengaluru, Karnataka. The role requires over 12 years of ASIC physical design experience and involves defining execution strategies for large programs, driving technology adoption, and overseeing chip-level closure plans.

The successful candidate will demonstrate excellent collaboration and communication skills, mentor teams, and manage EDA vendor relationships, ensuring successful tape-outs in a dynamic environment.

Qualifications

• Minimum 12 years of ASIC physical design experience.
• Experience in hiring, mentoring, and building expertise within a team.
• Excellent oral and written communication skills.

Responsibilities

• Define execution strategy for large programs.
• Drive new technology adoption and organization-wide improvements.
• Own the Chip-level PD closure plan and sign-off readiness reviews.

Skills

Collaboration

Teamwork

ASIC Physical Design

Flow Definition

EDA Vendor Management

Education

Master’s or Bachelor’s degree in Electronics/Electrical Engineering

Job description

MaxLinear is seeking a Senior Principal Physical Design Engineer with a minimum of 12 years of ASIC physical design experience. The role requires excellent collaboration, teamwork, hiring, mentoring, defining and driving flows and methodologies, resolving design and flow issues, working with front‑end teams, maintaining EDA vendor relationships, and delivering multiple successful tape‑outs in a dynamic environment.

Responsibilities

• Define execution strategy for large programs.
• Own full‑chip PD or major subsystems; define implementation strategy and ensure PPA targets and tape‑out readiness.
• Represent the team in program‑level forums and drive alignment across ASIC, EDA, layout, and program teams.
• Drive new technology adoption, flow definition, and organization‑wide improvements.
• Own the Chip‑level PD closure plan, sign‑off readiness reviews, escalation playbooks, tool/flow adoption plan, and org‑wide training artifacts.
• Deliver silicon for a wide range of applications.

Qualifications

• Minimum 12 years of ASIC physical design experience.
• Excellent collaboration and teamwork across various chip development disciplines.
• Experience in hiring, mentoring, and building expertise within a team.
• Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, and track progress.
• Experience resolving design and flow issues by identifying potential solutions and driving resolution.
• Experience working with front‑end teams to understand chip architecture and drive physical aspects early in the definition cycle.
• Experience managing relationships with EDA vendors.
• Multiple successful tape‑outs.
• Excellent oral and written communication skills.
• Ability to present to and interface with internal customers.
• Ability to handle a dynamic environment and coordinate team action.
• Master’s or Bachelor’s degree in Electronics/Electrical Engineering.