Senior Analog Layout Engineer

PI Semiconductor; Bengaluru; On-site; INR 2,400,000 - 3,600,000; Full time

Job summary

PI Semiconductor in Bengaluru, India, seeks a Senior Analog Layout Engineer to design high-performance layouts for analog, mixed-signal, and RF ICs. You will collaborate with circuit designers, process teams, and product groups to deliver silicon-proven layouts that meet aggressive performance, area, and schedule targets.

Responsibilities include full-chip and block-level layout for ADCs/DACs, floorplanning, place-and-route, and ensuring impedance, matching, EM/IR, ESD, and antenna compliance,

Qualifications

• 5+ years of hands-on analog/mixed-signal IC layout experience.
• Bachelor's or Master's degree in Electrical Engineering or Microelectronics.
• Strong expertise in Cadence Virtuoso; experience with Calibre or equivalent for DRC/LVS/PEX.

Responsibilities

• Own full-chip and block-level layout for analog/mixed-signal ICs (ADCs/DACs, bandgaps, LDOs, amplifiers, comparators).
• Translate schematics into layout with focus on matching, parasitics, noise isolation, EM/IR drop.
• Perform floorplanning, place & route strategy, and top-level integration for mixed-signal blocks.
• Work with circuit designers to apply layout techniques (symmetry, centroid, guard rings).
• Run/debug DRC, LVS, ERC, and parasitic extraction; close all physical verification checks.
• Collaborate with reliability/manufacturing to ensure EM/IR, ESD, antenna rules.
• Support post-layout simulation correlation and debug silicon layout issues.
• Mentor junior layout engineers and contribute to layout methodology and scripts.
• Interface with foundry/PDK teams on process updates and qualification.

Skills

Analog IC layout

Cadence Virtuoso

Calibre

Parasitic-aware layout

EM/IR and antenna rules

Education

Bachelor's or Master's in Electrical Engineering or Microelectronics

Tools

Calibre

PEX tools

Job description

About the Role

We are looking for a Senior Analog Layout Engineer to design and implement high-performance layouts for analog, mixed-signal, and RF integrated circuits. You will work closely with circuit designers, product engineers, and process/reliability teams to deliver silicon-proven layouts that meet aggressive performance, area, and schedule targets.

Key Responsibilities

• Own full-chip and block-level layout for analog/mixed-signal Ips like ADCs/DACs, bandgaps, LDOs, amplifiers, comparators.
• Translate schematics into layout while optimizing for matching, parasitics, noise isolation, and electromigration/IR drop.
• Perform floorplanning, place & route strategy, and top level integration for mixed-signal blocks.
• Work closely with circuit designers to understand design intent and apply appropriate layout techniques (symmetry, common centroid, guard rings, shielding).
• Run and debug DRC, LVS, ERC, and parasitic extraction (PEX); close all physical verification checks.
• Collaborate with design for reliability and design for manufacturing teams to ensure layout meets EM/IR, ESD, and antenna rules.
• Support post layout simulation correlation and help debug silicon issues related to layout.
• Mentor junior layout engineers and contribute to layout methodology, automation scripts, and best-practice documentation.
• Interface with foundry/PDK teams on process design kit updates and technology qualification.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics.
• 5+ years of hands-on analog/mixed-signal IC layout experience.
• Strong expertise in Cadence Virtuoso (or similar layout tools); experience with Calibre or equivalent for DRC/LVS/PEX.
• Solid understanding of analog layout techniques: matching, symmetry, shielding, guard-ringing, ESD, and noise-sensitive routing.
• Familiarity with parasitic-aware layout and post-layout simulation correlation.
• Strong understanding of EM/IR, antenna rules, and reliability driven layout practices.
• Good communication skills and ability to work cross functionally with design, verification, and product teams.