Analog Layout Design Engineer

UST; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

UST in Bengaluru, India seeks a skilled Analog Layout Engineer to join our semiconductor design team. The candidate will implement analog and mixed-signal layouts for high-performance devices, ensuring design rule adherence and manufacturability.

You will collaborate with circuit designers and foundries to optimize matching, shielding, and parasitics, and participate in post-layout signoff activities to meet performance and schedule targets.

Qualifications

• 4+ years of hands-on analog/mixed-signal layout experience.
• Experience with high-performance analog circuits and RF blocks.
• Familiarity with layout checks and signoff processes.

Responsibilities

• Layout analog, mixed-signal, and RF blocks for advanced technologies.
• Ensure matching, symmetry, shielding, and parasitic optimization.
• Conduct floorplanning and placement of analog blocks.
• Perform DRC, LVS, ERC, antenna, and density checks.
• Extract parasitics and support post-layout simulations.
• Collaborate with circuit designers, verification engineers, and foundry teams.
• Debug and resolve layout-related issues to meet performance and schedule targets.
• Follow foundry guidelines and process-specific requirements.

Skills

Analog Layout

Mixed-Signal

RF Layout

DRC/LVS/ERC

Floorplanning

Post-layout Signoff

Foundry Collaboration

Device Matching

Job description

Position: Analog Layout Engineer

Experience: 4+ Years

Job Summary

We are seeking a highly motivated Analog Layout Engineer to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal circuits, ensuring compliance with technology design rules, matching requirements, and manufacturability constraints.

Key Responsibilities

• Develop and implement custom analog, mixed-signal, and RF layouts for advanced semiconductor technologies.
• Perform layout of critical analog blocks such as:
• Operational Amplifiers (Op-Amps)
• Bandgap References
• LDO Regulators
• PLLs
• ADCs/DACs
• Charge Pumps
• Data Converters
• Ensure proper device matching, symmetry, shielding, and parasitic optimization.
• Conduct floorplanning and placement of analog blocks.
• Perform layout verification activities:
• DRC (Design Rule Check)
• LVS (Layout Versus Schematic)
• ERC (Electrical Rule Check)
• Antenna Checks
• Density Checks
• Extract parasitics and support post-layout simulation and signoff activities.
• Collaborate closely with circuit designers, verification engineers, and foundry teams.
• Debug and resolve layout-related issues to meet performance, area, and schedule targets.
• Follow foundry design guidelines and process-specific requirements.