Senior Analog Layout Engineer

LeadSoc Technologies Pvt Ltd; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Hyderabad is seeking a Senior Analog Layout Engineer to deliver high-quality layouts for complex analog and mixed-signal blocks, collaborating with circuit designers to meet performance, matching, reliability, and area objectives.

The role involves developing custom analog/mixed-signal layouts from schematic to physical database, using Cadence Virtuoso, applying matching and guard-ring techniques, and supporting top-level integration and flow improvements.

Qualifications

• 4-8 years of relevant experience in Analog/Custom IC Layout.
• Strong hands-on experience with Cadence Virtuoso.
• Good understanding of CMOS analog layout techniques and advanced matching concepts.
• Experience with DRC, LVS, ERC and PEX.
• Strong understanding of device physics, parasitics and layout-dependent effects.
• Experience with deep-submicron/advanced-node technologies is preferred.
• Good exposure to analog/mixed-signal IC design flows.
• Ability to independently own blocks from layout initiation through signoff.
• Strong debugging and problem-solving skills.

Responsibilities

• Develop custom analog and mixed-signal layouts from schematic/netlist to physical database.
• Layout of analog blocks such as amplifiers, bandgaps, LDOs, ADC/DAC blocks, PLLs, references, and bias circuits.
• Apply matching techniques including matching, common-centroid, interdigitation, shielding, guard rings, and dummy structures.
• Perform DRC, LVS, ERC and PEX and resolve layout-related issues.
• Collaborate closely with Analog Design, Circuit Design, Verification and Physical Design teams.
• Optimize layout for area, parasitics, matching, noise and overall circuit performance.
• Analyze and address post-layout simulation and extraction-related issues.
• Support top-level/custom block integration and physical verification closure.
• Contribute to layout methodology, automation and flow improvements.

Skills

Analog/Custom IC Layout

Cadence Virtuoso

CMOS analog layout

DRC LVS PEX ERC

Device physics & parasitics

Deep-submicron tech

Analog/mixed-signal flows

Block-level signoff ownership

Debugging & problem solving

Tools

Cadence Virtuoso

Job description

We are looking for a Senior Analog Layout Engineer with strong hands-on experience in custom/analog IC layout. The ideal candidate will be responsible for delivering high-quality layouts for complex analog and mixed-signal blocks while working closely with circuit designers to achieve performance, matching, reliability, and area objectives.

Key Responsibilities

• Develop custom analog and mixed-signal layouts from schematic/netlist to physical database.
• Work on layout of analog blocks such as amplifiers, bandgaps, LDOs, ADC/DAC blocks, PLLs, references, and bias circuits.
• Apply advanced layout techniques including matching, common-centroid, interdigitation, shielding, guard rings, and dummy structures.
• Perform DRC, LVS, ERC and PEX and resolve layout-related issues.
• Collaborate closely with Analog Design, Circuit Design, Verification and Physical Design teams.
• Optimize layout for area, parasitics, matching, noise and overall circuit performance.
• Analyze and address post-layout simulation and extraction-related issues.
• Support top-level/custom block integration and physical verification closure.
• Contribute to layout methodology, automation and flow improvements.

Required Skills

• 4-8 years of relevant experience in Analog/Custom IC Layout.
• Strong hands-on experience with Cadence Virtuoso.
• Good understanding of CMOS analog layout techniques and advanced matching concepts.
• Experience with DRC, LVS, ERC and PEX.
• Strong understanding of device physics, parasitics and layout-dependent effects.
• Experience with deep-submicron/advanced-node technologies is preferred.
• Good exposure to analog/mixed-signal IC design flows.
• Ability to independently own blocks from layout initiation through signoff.
• Strong debugging and problem-solving skills.

Preferred

• Experience with high-performance analog, mixed-signal, PMIC, SerDes, PLL or data-converter layouts.
• Exposure to FinFET/GAA or advanced CMOS processes.
• Experience with EM/IR, reliability and post-layout simulation.
• Scripting/automation experience using SKILL, Tcl or Python is a plus.
• Strong communication and cross-functional collaboration skills.