Ams Verification Engineer

Exiger Technologies; Bengaluru; Hybrid; INR 1,800,000 - 3,000,000; Full time

Job summary

Exiger Technologies in Bengaluru seeks an experienced AMS Verification engineer to lead verification across mixed-signal IPs.

You will own verification efforts from specification review through sign-off, developing wreal models for analog blocks and collaborating with Analog Design and Digital teams to optimize circuit intent and abstractions.

Qualifications

• 46 years of hands-on experience in AMS Verification.
• Strong expertise in Verilog-AMS.
• Strong knowledge of SystemVerilog.
• Hands-on experience with wreal modeling.
• Experience with Xcelium AMS and/or VCS AMS.
• Good understanding of mixed-signal verification.
• Strong debugging and root-cause analysis skills.

Responsibilities

• Own AMS verification for assigned IPs/subsystems from specification review through sign-off.
• Develop and maintain wreal models for analog blocks.
• Work closely with Analog Design and Digital teams to understand circuit intent and abstraction trade-offs.
• Analyze failures across analog and digital domains and drive root-cause resolution.
• Review and improve existing AMS testbenches and models.
• Contribute to coverage closure, waiver reviews, and sign-off documentation.
• Ensure verification quality across mixed-signal IPs.

Skills

AMS verification

Verilog-AMS

SystemVerilog

wreal modeling

Xcelium AMS

VCS AMS

mixed-signal verification

debugging

Tools

Xcelium AMS

VCS AMS

Job description

Key Responsibilities

• Own AMS verification for assigned IPs/subsystems from specification review through sign-off.
• Develop and maintain wreal models for analog blocks.
• Work closely with Analog Design and Digital teams to understand circuit intent and abstraction trade-offs.
• Analyze failures across analog and digital domains and drive root-cause resolution.
• Review and improve existing AMS testbenches and models.
• Contribute to coverage closure, waiver reviews, and sign-off documentation.
• Ensure verification quality across mixed-signal IPs.

Candidate Profile

• 46 years of hands-on experience in AMS Verification
• Strong expertise in Verilog-AMS
• Strong knowledge of SystemVerilog
• Hands-on experience with wreal modeling
• Experience with Xcelium AMS and/or VCS AMS
• Good understanding of mixed-signal verification
• Strong debugging and root-cause analysis skills