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Source-Right is seeking an experienced DFT engineer for high-performance chip designs focusing on scan-based logic test, memory test and repair, boundary scan, and high-speed interface testing. You will develop DFT methodologies and coordinate with front-end and back-end teams to integrate features.
You will use industry-standard tools for DFT implementation, pattern generation, simulation and verification, and help with ATE pattern delivery and silicon bring-up.
Position: SCAN DFT, ATPG, Diagnostic, Coverage Analysis (BB612FT RM 4438)
The DFT Engineer is responsible for Hardware Design-For-Test (DFT) activities for high-performance chip designs to enable efficient high-coverage Test. This includes scan-based logic test, memory test and repair, boundary scan, and high-speed interface testing. The engineer will develop appropriate DFT methodology and flows, and work with the front-end design team to integrate and flush new DFT features & methodologies into the design and document the DFT architecture. The engineer will work on Industry-standard tools for DFT implementation, Pattern generation, Simulation and verification of the DFT features. The engineer will interface with the back-end team on timing, physical design and with the PDTE team on ATE pattern delivery & ATE silicon bring up.