ASIC/SoC Design Engineer

Modernize Chip Solutions (MCS); Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Modernize Chip Solutions (MCS) in Hyderabad, India seeks an experienced ASIC/SoC Design Engineer to lead RTL design, micro-architecture development, and integration across the full ASIC lifecycle. You will work with cross-functional teams to deliver high-performance, silicon-ready designs, with emphasis on synthesis, timing closure, and prototyping.

Hands-on RTL design experience, exposure to interface protocols, FPGA-based prototyping, and a completed ASIC tape-out are highly valued in this

Qualifications

• 8+ years experience in ASIC/SoC design or equivalent.
• Hands-on RTL design and Verilog coding experience.
• Exposure to advanced interface protocols and FPGA-based prototyping.
• Experience with at least one ASIC tape-out is required.

Responsibilities

• Design and implement complex ASIC/SoC architectures and RTL blocks.
• Develop micro-architecture specifications, synthesizable RTL, and documentation.
• Perform RTL synthesis, timing analysis, and timing closure to hit targets.
• Optimize designs for power, performance, and bandwidth.
• Collaborate with FPGA teams on prototyping and validation.
• Support test program development, chip validation, and production readiness.
• Coordinate with Architecture, Verification, SoC Integration, DFT, Physical Design, FPGA, Firmware, and Software teams.

Skills

RTL Design

Micro-Architecture

SoC Integration

Synthesis

Timing Closure

FPGA Prototyping

Interface Protocols

Verification Fundamentals

Scripting

ASIC Tape-out

PCIe

USB

Ethernet

I2C/I3C

SPI

UART

eMMC/SD

Tools

HAPS

Veloce

Job description

Experience: 8+ Years

Core Skills: RTL Design | Micro-Architecture | SoC Integration | Synthesis | Timing Closure | FPGA Prototyping

About the Role

We are looking for an experienced ASIC/SoC Design Engineer with strong expertise in RTL design, micro-architecture development, SoC integration, synthesis, and timing optimization.

In this role, you will contribute to the development of complex SoCs across the ASIC design lifecycle, collaborating with cross-functional teams to deliver high-performance, power-efficient, and silicon-ready designs.

If you have hands-on RTL design experience, exposure to advanced interface protocols, FPGA-based prototyping, and at least one completed ASIC tape-out, we'd love to connect with you!

Key Responsibilities

• Design and implement complex ASIC/SoC architectures and RTL blocks.
• Develop micro-architecture specifications, synthesizable RTL, and technical documentation.
• Perform RTL synthesis, timing analysis, and timing closure to meet performance targets.
• Optimize block-level and top-level designs for power, performance, and bandwidth.
• Collaborate with FPGA teams on prototyping, emulation, and early design validation.
• Support test program development, chip validation, silicon maturation, and production readiness.
• Work closely with Architecture, Design Verification, SoC Integration, DFT, Physical Design, FPGA, Firmware, and Software teams throughout the ASIC development lifecycle.

Required Technical Skills

• RTL Design: Strong hands-on experience in Verilog RTL coding and logic design.
• Micro-Architecture: Ability to develop clear, efficient, and implementable micro-architecture specifications.
• SoC Integration: Experience integrating complex IPs and interface protocols.
• Synthesis & Timing: Good understanding of RTL synthesis, timing analysis, and timing closure.
• Verification Fundamentals: Knowledge of assertions, functional coverage, and RTL verification concepts.
• Interface Protocols: Experience with one or more of the following:
• PCIe, USB, and Ethernet
• DDR3/DDR4 and LPDDR
• I2C/I3C, SPI, and UART
• SD/SDIO and eMMC
• FPGA Prototyping: Experience with FPGA-based emulation and prototyping platforms such as HAPS or Veloce.
• Scripting: Proficiency in Perl and/or Python scripting.
• ASIC Tape-out: Must have completed at least one ASIC tape-out cycle.

Preferred Qualifications

• Hands-on experience in silicon bring-up and post-silicon debugging.
• Familiarity with version control and CI tools such as Bitbucket and Jenkins.
• Experience with issue tracking tools such as JIRA.

Why This Opportunity?

• Work on complex ASIC/SoC design challenges.
• Collaborate with cross-functional engineering teams across the silicon development lifecycle.
• Contribute to RTL implementation, performance optimization, FPGA prototyping, and silicon readiness.
• Apply your expertise to real-world chip design and tape-out activities.

Join us and be part of the next generation of ASIC/SoC innovation!