RTL Design Engineer

ACL Digital; Bengaluru; On-site; INR 800,000 - 1,600,000; Full time

Job summary

ACL Digital is seeking a Mid-Senior level Design Engineer with strong expertise in RTL Design using Verilog/System Verilog and hands-on experience in SoC/ASIC design and integration. This full-time role in the Semiconductor Manufacturing industry offers an opportunity to enhance your capabilities while contributing to cutting-edge projects.

Qualifications

• Strong experience in RTL Design using Verilog/System Verilog.
• Hands-on experience with complex SoC/ASIC design and synthesis.

Skills

RTL Design

Verilog/System Verilog

SoC/ASIC Design

Synthesis

Lint

CDC

Job description

Direct message the job poster from ACL Digital.

Requirements:

• Strong experience in RTL Design using Verilog/System Verilog.
• Exposure to complex SoC/ASIC design and integration.
• Hands-on experience with synthesis, Lint, CDC preferred.

Please share your resume at [e-mail].

Details:

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Industry: Semiconductor Manufacturing

Note: Referrals increase your chances of interviewing at ACL Digital by 2x.

Sign in to set job alerts for “Design Engineer” roles.

Additional info:

Research Development Mechanical Engineer

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.