Rtl Design Engineer

Omniglobe International; Hyderabad, Chennai, Bengaluru; Híbrido; INR 1.200.000 - 2.000.000; Jornada completa

Descripción de la vacante

Omniglobe International in Hyderabad, Telangana, India seeks an ASIC RTL Design Engineer with 4 years of experience to drive high-quality RTL development for cutting-edge SoC projects.

You will work on Verilog/SystemVerilog RTL, perform lint and CDC analysis, support synthesis and timing closure, and collaborate with Architecture, Verification, and Physical Design teams to integrate IPs.

Formación

• 4 years of experience in RTL design for ASIC/SoC.
• B.Tech degree or equivalent is required.
• Relevant industry experience or internship accepted.

Responsabilidades

• Develop high-quality, synthesizable RTL for ASIC designs
• Perform Lint and CDC analysis and resolve violations
• Support synthesis and timing closure activities
• Work closely with Architecture, Verification, and Physical Design teams
• Integrate IPs into SoC and debug functional/design issues
• Contribute to high-performance, low-power ASIC development

Conocimientos

RTL Design

Digital Design & SoC

SpyGlass CDC

Educación

B.Tech

Herramientas

SpyGlass Lint

CDC

Descripción del empleo

We're hiring an ASIC RTL Design Engineer with 04 years of experience. B.Tech graduates from 2023 or earlier only (Relevant Industry experience OR Internship experience also works).

Join our growing semiconductor team and work on cutting-edge ASIC, SoC Design, RTL Development, CDC Analysis, and IP Integration projects.

What We're Looking For:

• Strong RTL Design skills using Verilog/SystemVerilog


• Good understanding of Digital Design, Micro-architecture, and SoC Design


• Hands-on experience with SpyGlass Lint & CDC

Key Responsibilities:

• - Develop high-quality, synthesizable RTL for ASIC designs


• - Perform Lint and CDC analysis and resolve violations


• - Support synthesis and collaborate on timing closure activities


• - Work closely with Architecture, Verification, and Physical Design teams


• - Integrate IPs into SoC and debug functional/design issues


• - Contribute to high-performance, low-power ASIC development