RTL Design Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru, India, is seeking an experienced ASIC Design Engineer to join our silicon engineering team. You will contribute across the full ASIC development lifecycle, focusing on high-speed interfaces and digital design.

The ideal candidate has deep expertise in PCIe, Ethernet, USB, or SerDes-based interfaces, strong Verilog/SystemVerilog RTL skills, and a track record of timing closure and IP integration in complex SoCs.

Qualifications

• Experience in ASIC/SoC design with high-speed protocols.
• RTL development in Verilog/SystemVerilog with performance, power and area focus.
• Define micro-architecture and interface specs for protocol IPs.
• Collaborate with verification and physical design teams for timing and bring-up

Responsibilities

• Architect and design high-performance digital blocks for ASIC/SoC with high-speed protocols.
• Develop RTL in Verilog/SystemVerilog emphasizing performance, power and area.
• Define micro-architecture and interface specs for protocol IPs.
• Collaborate with verification to develop test plans and ensure coverage.
• Work with physical design teams for synthesis, timing closure and floorplanning.
• Analyze and debug silicon bring-up issues for high-speed interfaces.
• Integrate third-party IPs (SerDes, PHYs) and ensure interoperability.
• Participate in design reviews and enforce best practices.

Skills

ASIC design

Verilog/SystemVerilog

High-speed protocols

Micro-architecture

Timing closure

Job description

We are seeking an experienced ASIC Design Engineer with deep expertise in high-speed interface protocols to join our silicon engineering team. The ideal candidate will have a strong background in digital design, micro-architecture, and implementation of high-speed protocols such as PCIe, Ethernet, USB, or SerDes-based interfaces, and will contribute across the full ASIC development lifecycle.

1. Architect and design high-performance digital blocks for ASIC/SoC targeting high-speed protocols (e.g., PCIe Gen4/5, 100G/400G Ethernet, USB3/4).

2. Develop RTL using Verilog/SystemVerilog with a focus on performance, power, and area optimization.

3. Define micro-architecture and interface specifications for protocol IPs.

4. Collaborate with verification teams to develop test plans, debug failures, and ensure coverage closure.

5. Work closely with physical design teams for synthesis, timing closure, and floorplanning support.

6. Analyze and debug silicon bring-up issues related to high-speed interfaces.

7. Integrate third-party IPs (SerDes, PHYs) and ensure proper functionality and interoperability.

8. Participate in design reviews and ensure adherence to design methodologies and best practices.