Digital Design, Senior Engineer

Synopsys, Inc.; India; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Synopsys, Inc. in India seeks a Senior ASIC Digital Design Engineer to own RTL for PCIe IP, collaborating with staff and principal engineers. You will implement designs from specs, debug in simulation, and help drive timing and power considerations across the design flow.

The role emphasizes high-speed interfaces, clocking, FSMs, and synthesizable SystemVerilog, with mentoring from senior staff. A strong RTL mindset and collaborative approach are essential.

Qualifications

• BS/BE in Electrical Engineering or related field with strong RTL background.
• Experience delivering high-speed PCIe IP blocks or SoC components.
• Hands-on ASIC RTL design in SystemVerilog for production designs.
• Understanding of clocks, resets, state machines and pipelines.

Responsibilities

• Implement and own RTL for PCIe blocks from micro-architecture specs.
• Debug design issues in simulation and bring-up environments as needed.
• Contribute to micro-architecture discussions and document intent.
• Enforce RTL coding standards, lint/CDC hygiene, and review closures.
• Collaborate with verification to define coverage and fix root causes.
• Support synthesis, timing, and low-power feedback from physical design.
• Mentor junior engineers toward broader subsystem ownership.

Skills

RTL design

SystemVerilog

PCIe

Clocking/Reset/FSM

Pipelines

Debugging

Verification collaboration

Scripting (Python/TCL/Perl)

AI-assisted tools

Education

BSEE

MSEE

Tools

SystemVerilog tooling

Simulation

Synthesis

Emulation

Lint/CDC

Job description

ASIC Digital Design Engineer, Senior

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.

You Are:
You are a Senior ASIC Digital Design Engineer who delivers high-quality RTL for complex PCIe IP. You take a spec or micro-architecture, implement it cleanly, debug it thoroughly, and stand behind the block you own.

You have proven digital design experience on SoC or IP, ideally high-speed interfaces. You understand clocks, resets, state machines, pipelines, and synthesizable coding practice. PCIe experience is a strong plus; equivalent protocol or data-path experience is welcome.

You work closely with Staff and Principal engineers for your assigned subsystem features. You contribute in reviews, write maintainable RTL, and help verification reproduce and close issues.

What You'll Be Doing:

• Implement and own RTL for PCIe blocks and features from micro-architecture and design specs.
• Debug design issues in simulation and, as needed, in formal, emulation, or silicon bring-up support.
• Contribute to micro-architecture discussions for your blocks; document design intent and corner cases.
• Follow and help enforce RTL coding standards, lint/CDC hygiene, and review comments to closure.
• Work with verification to define coverage intent, root-cause failures, and deliver fixes on schedule.
• Support synthesis, timing, and low-power feedback from physical design for your blocks.
• Develop toward broader subsystem ownership with mentoring from Staff and Principal engineers.

The Impact You Will Have:

• Deliver quality, maintainable RTL for silicon-proven PCIe IP.
• Improve execution speed and quality on assigned features
• Be part of Synopsys PCIe controller team delivering high-speed interface IP to leading customers.

What You'll Need:

• BSEE with 5+ years of relevant experience, or MSEE with 3+ years (or equivalent).
• Hands-on ASIC RTL design in SystemVerilog on production designs.
• Experience with at least one of: PCIe, CXL, AMBA/AXI, DDR, Ethernet, or other high-speed / on-chip interconnect data paths.
• Working knowledge of clocking, resets, FSMs, pipelines, and synthesizable design practice.
• Familiarity with simulation debug; lint, CDC, or synthesis exposure is a plus.
• Scripting (Python, TCL, Perl) and AI-assisted design tools are a plus.

Who You Are:

• A strong RTL engineer with quality mindeset who finishes what they own.
• Responsive in reviews and debug.
• Curious about protocol and micro-architecture