Field-Programmable Gate Arrays Engineer

TechBliss Digital Solution Pvt. Ltd.; Gurugram District; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

A leading technology solutions provider is looking for an FPGA Engineer with over 7 years of experience in high-speed FPGA development. The ideal candidate should have a strong background in high-speed serial protocols such as PCIe and NVMe, as well as expertise in using tools like Xilinx Vivado for design and implementation. Responsibilities include designing FPGA logic, solving complex design challenges, and collaborating with global teams. This role offers a chance to work on cutting-edge technologies and contribute to innovative projects.

Qualifications

• More than 7 years of FPGA design and development experience is required.
• Strong expertise in high-speed FPGA design and protocol validation.
• Hands-on experience with FPGA synthesis/implementation tools is essential.

Responsibilities

• Design and develop FPGA RTL logic for high-speed serial protocols.
• Solve FPGA design challenges related to timing closure and interface performance.
• Collaborate with R&D teams globally for FPGA solution delivery.

Skills

Experience in high-speed FPGA development

Expertise in high-speed serial protocols

Knowledge of FPGA tools (Xilinx Vivado)

Familiarity with ModelSim and Que

Job description

Overview

We are seeking an FPGA Engineer with strong expertise in high-speed serial protocol-based designs. The ideal candidate is smart, energetic, and hands-on, with proven experience in high-speed FPGA development and the ability to solve complex design challenges. Preferred protocols: PCIe, NVMe, and CXL. Other valuable experience: Ethernet (10G/25G/100G), USB 3.x/USB4, SATA, SAS, InfiniBand, DisplayPort, HDMI, MIPI M-PHY.

Responsibilities

• Design, architect, and develop FPGA RTL (VHDL/Verilog) logic and subsystems for highspeed serial protocols.
• Address FPGA design challenges such as CDC, multi-clock domains, timing closure, and SerDes-related issues.
• Drive timing closure and optimization using FPGA synthesis and implementation tools (Xilinx Vivado).
• Debug and validate FPGA and board-level issues, ensuring robust high-speed interface performance.
• Collaborate with global R&D teams to deliver production-ready FPGA solutions.
• Leverage AI-assisted tools (e.g., GitHub Copilot, LLM-based aids) to accelerate RTL development and productivity.

Requirements

• 7+ years of FPGA design and development experience.
• Strong expertise in high-speed serial protocols (PCIe, NVMe, CXL preferred; others such as Ethernet, USB 3.x/USB4, SATA, SAS, InfiniBand, DisplayPort, HDMI, or MIPI M-PHY also acceptable).
• Proven skills in high-speed FPGA design, including CDC handling, timing closure, and interface validation.
• Hands-on experience with FPGA synthesis/implementation tools (Xilinx Vivado: synthesis, place-and-route, timing closure, on-board debug).
• Experience with FPGA simulation tools (ModelSim, Que)