An innovative firm is seeking a skilled RTL designer with expertise in Verilog/System Verilog and front-end design tools. This role involves developing micro architectures from specifications, implementing synthesis and timing analysis, and working on low power synthesis while ensuring compliance with standard coding guidelines. You will be part of a dynamic team that tackles complex challenges in IP and SOC level synthesis across various process technologies. If you are passionate about RTL design and eager to contribute to cutting-edge projects, this opportunity is perfect for you.
Qualifications
Strong knowledge of RTL design and Verilog/System Verilog.
Experience in low power synthesis and UPF understanding.
Responsibilities
Develop micro architecture from specifications to RTL coding.
Work on IP and SOC level synthesis across multiple generations.
Skills
RTL design
Verilog/System Verilog
Synthesis
Timing Analysis
Micro architecture development
Low power synthesis
UPF
AMBA AHB/AXI protocol
ECO implementation
Tools
Front-end design tools
Code coverage tools
Lint
CDC Formality
Job description
Sound knowledge of RTL design with Verilog/System Verilog and front-end design tools & flows.
Good experience in Synthesis & Timing Analysis required.
Experience in developing Micro architecture from specifications and taking it up to RTL coding and synthesis.
Should have worked on IP and SOC level Synthesis for multiple generations and be familiar with problems associated with different Process technologies.
Should have experience working on Low power synthesis and understand UPF.
Experience in implementing ECOs.
IP development and coding using standard coding guidelines.
Must have strong knowledge of AMBA AHB/AXI protocol.
Working knowledge of code coverage, functional coverage, Lint, CDC Formality, etc.