Principal IP verification engineer

NXP Semiconductors; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

NXP Semiconductors in Bengaluru is looking for an experienced IP Verification Engineer - Principal. The role involves verifying complex IPs involving memory controllers and interconnects while collaborating with global design and architecture teams.

The ideal candidate must have over 10 years of experience in verification, strong knowledge of SystemVerilog, UVM, and good understanding of interconnect protocols. The position offers a challenging work environment and opportunities for collaboration across teams.

Qualifications

• 10+ years of experience in IP verification.
• Strong expertise in SystemVerilog, UVM, and Verilog.
• Good understanding of functional verification methodologies and coverage.

Responsibilities

• Develop and execute verification plans for memory controllers and interconnects.
• Build scalable SystemVerilog/UVM-based verification environments.
• Own end-to-end IP verification sign-off.

Skills

SystemVerilog

UVM

Verilog

Functional verification methodologies

Interconnect protocols (AXI, AHB, CHI, PCIe)

Debugging complex RTL

Job description

IP verification engineer - Principal

In this role you will be responsible for verifying complex IPs involving memory controllers and interconnects, collaborating with global design and architecture teams.

Key Responsibilities

• Develop and execute verification plans for memory controllers, interconnects and other infrastructural IPs.
• Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards).
• Own end-to-end IP verification sign-off.
• Achieve high-quality metrics including functional coverage and code coverage.
• Manage regressions and debug failures.
• Collaborate closely with design teams to resolve issues.

Required Expertise

Experience: 10+ years

• Strong experience in SystemVerilog, UVM, and Verilog.
• Good understanding of Functional verification methodologies, Assertions (SVA) and coverage.
• Good understanding of interconnect protocols such as AXI, AHB, CHI and PCIe.
• Experience debugging complex RTL and testbench issues.
• Experience in Formal verification is an added plus.