Job Posting Title Principal ASIC Design Verification Engineer

MaxLinear, Inc.; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

MaxLinear, Inc. is seeking a Principal ASIC Design Verification Engineer in Bengaluru, India. The ideal candidate will provide technical leadership and strategic direction across IP, Subsystem, and SoC verification and must have 12-16 years of hands-on ASIC Design Verification experience. The role requires expertise in SystemVerilog, UVM, and high-speed protocols. Responsibilities include defining verification strategies, mentoring engineers, and driving AI-assisted verification solutions to enhance productivity across complex ASIC platforms.

Qualifications

• 12–16 years of deep, hands-on ASIC Design Verification experience.
• Demonstrated leadership in IP, Subsystem, and SoC-level verification.
• Proven success applying AI-assisted verification techniques.

Responsibilities

• Act as a verification technical leader and architect across various programs.
• Define end-to-end verification strategies and best practices.
• Mentor senior and junior verification engineers.

Skills

SystemVerilog

UVM

Verilog

C/C++

Python

Education

Bachelor’s or Master’s degree in Electronic Engineering or a related field

Tools

Linux/Unix environments

high-speed protocols (Ethernet, PCIe, USB 3.0, SERDES)

Job description

Responsibilities

We are seeking a Principal ASIC Design Verification Engineer to provide technical leadership and strategic direction across IP, Subsystem, and SoC verification. This role is ideal for a verification architect and technical authority who drives methodology innovation, mentors teams, and champions AI-assisted verification to scale quality and productivity across complex ASIC platforms. You will focus on the following:

• Act as a verification technical leader and architect across IP, Subsystem, and SoC programs
• Define and own end-to-end verification strategies, methodologies, and best practices across teams
• Architect highly reusable, scalable, and modular UVM-based verification environments
• Drive cross-project alignment on verification flows, coverage strategies, and sign-off criteria
• Lead complex debug efforts, root‑cause analysis, and final functional sign‑off for critical programs
• Champion AI‑driven, data‑driven, and automation‑enabled verification solutions to eliminate bottlenecks
• Establish advanced regression, coverage analytics, and intelligent failure triage workflows
• Mentor senior and junior verification engineers; raise the overall technical bar of the organization
• Partner closely with architecture, design, validation, and product teams to influence design‑for‑verification decisions
• Act as a key technical interface with internal leadership and external stakeholders

Qualifications

• Bachelor’s or Master’s degree in Electronic Engineering or a related field
• 12–16 years of deep, hands‑on ASIC Design Verification experience
• Demonstrated leadership in IP, Subsystem, and SoC‑level verification, preferably in networking or packet‑processing domains
• Proven experience architecting complex verification environments used across multiple programs
• Expert‑level skills in:
• SystemVerilog, UVM, Verilog
• C/C++
• Strong mastery of verification methodologies, including constrained‑random, coverage‑driven verification, and gate‑level simulations
• Extensive experience in Linux/Unix environments; strong scripting skills (Python preferred)
• Hands‑on expertise with high‑speed protocols such as Ethernet, PCIe, USB 3.0, and SERDES
• Experience with SystemC and DSP concepts is highly desirable
• Proven success applying AI‑assisted verification techniques for debug acceleration, coverage optimization, and productivity gains
• Strong technical influence, communication, and mentorship skills with a strategic mindset