Principal DFT Engineer

Cadence; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Cadence in Bengaluru seeks an experienced SoC/ASIC DFT engineer. The role focuses on Design for Test, ATPG, and scan technologies to achieve high fault coverage. Collaboration with cross‑functional teams and independent task ownership are key.

Responsibilities include inserting compression scan, LBIST, MBIST, and ensuring ATPG bench verification meets design goals in a fast-paced project environment.

Qualifications

• Extensive experience in SoC/ASIC Digital Design with emphasis on DFT.
• Hands-on knowledge of DFT insertion flows and scan chain techniques.
• Proficient in ATPG and achieving design fault coverage targets.

Responsibilities

• Lead design-for-test activities for SoC/ASIC projects.
• Insert compression scan, LBIST and other scan technologies.
• Verify ATPG testbenches and debug mis‑comparisons in simulations.
• Use JTAG 1149.1/6, IEEE 1500 and IEEE 1687 in test environments.
• Collaborate with Architecture, Design, and Customer teams to meet goals.
• Independently complete DFT tasks and drive issue resolution.

Skills

DFT insertion flows

Design for Test

ATPG

LBIST

MBIST

JTAG 1149.1/6

IEEE 1500

IEEE 1687

Cadence tools

Cross-functional collaboration

Debugging testbenches

Fault analysis

Timing analysis knowledge

Tools

Cadence tools

Job description

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Prior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
• Should possess intimate knowledge of DFT insertion flows
• Basic scan chain insertion using synthesis or other software tools
• Experience in compression scan insertion, LBIST and other scan technologies
• Intimate knowledge of memory built-in self-test (MBIST)
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
• Debug and analysis of failures to improve fault coverage
• Verification of ATPG testbenches and debugging root cause of simulation mis‑compares
• Working knowledge of JTAG 1149.1/6, IEEE 1500 and IEEE 1687
• Knowledge of timing analysis and equivalency checks would be a plus
• Ability to work in a collaborative team environment
• Prior experience with Cadence tools and flows is highly desirable
• Should be able to complete DFT tasks independently
• Strong problem-solving skills, with discipline, thoroughness, and a methodical approach
• Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
• Self-driven and committed to working in a fast-paced project environment