Principal DFT Engineer

Jobtailor; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Jobtailor in Bengaluru seeks an experienced DFT Engineer to lead scan architectures, ATPG, and GLS validation for robust silicon signoff. You will collaborate with RTL, physical design, and test teams to ensure high fault coverage and timely tape-out support.

The role demands deep hands-on DFT expertise and strong Verilog/SystemVerilog skills. Ideal candidates have 7–12 years of DFT experience, proficiency with Mentor Tessent, Synopsys, and Cadence, and the ability to troubleshoot DFT/GLS issues

Qualifications

• 7-12 years of experience in DFT Engineering.
• Strong hands-on expertise in Scan Insertion, ATPG, and GLS.
• Proficiency with industry-standard DFT tools: Mentor Tessent, Synopsys, Cadence.
• Solid Verilog/SystemVerilog skills.
• Ability to debug DFT and GLS issues independently.
• Prior experience supporting pre- and post-silicon activities is a plus.

Responsibilities

• Implementing and verifying scan architectures.
• Performing scan insertion.
• Generating and analyzing ATPG patterns for stuck-at and transition faults.
• Executing GLS with and without SDF for DFT validation.
• Collaborating with RTL, physical design, and test teams to ensure high fault coverage.
• Ensuring clean DFT signoff and timely tape-out support.

Skills

Scan Insertion

ATPG

Gate-Level Simulation

Verilog/SystemVerilog

DFT debugging

Tools

Mentor Tessent

Synopsys

Cadence

Job description

Responsibilities

• Implementing and verifying scan architectures
• Performing scan insertion
• Generating and analyzing ATPG patterns for stuck‑at and transition faults
• Executing GLS with and without SDF for DFT validation
• Collaborating with RTL, physical design, and test teams to ensure high fault coverage
• Ensuring clean DFT signoff and timely tape‑out support

Requirements

• 7-12 years of experience in DFT Engineering
• Strong hands‑on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS)
• Proficiency with industry‑standard DFT tools (Mentor/Siemens Tessent, Synopsys, Cadence)
• Solid Verilog/SystemVerilog skills
• Ability to debug DFT and GLS issues independently
• Prior experience supporting pre- and post-silicon activities is a plus