Principal ASIC Design Engineer

Nokia; Bengaluru; Presencial; INR 3 500 000 - 7 000 000; Tempo integral

Resumo da oferta

Nokia in Bengaluru is seeking a senior ASIC design Lead to own end-to-end development of a major ASIC function from requirements through silicon qualification. The role demands deep microarchitecture expertise, RTL design skills, and strong technical leadership in a deep submicron process.

You will mentor a team of designers, drive planning and implementation, and collaborate with verification and lab teams to ensure successful silicon bring-up and validation.

Qualificações

• Bachelor's degree or higher in CS or EE with very good academics.
• 10+ years of experience delivering a major function/ASIC.
• Preferred: Ethernet/Networking domain experience.

Responsabilidades

• Own end-to-end ASIC development from requirements to silicon qualification.
• Lead microarchitecture definition and RTL design.
• Provide technical leadership to a team of designers and drive planning, definition and implementation.
• Oversee lint, CDC, RDC, synthesis and timing reports.
• Collaborate with verification and lab validation teams to qualify the implementation.

Conhecimentos

RTL design

Technical leadership

Low-power design

AMS verification

Clock domain crossing

Formação académica

Bachelor's degree in CS or EE

Master's degree preferred

Ferramentas

Synopsys tools

Cadence tools

Mentor tools

Descrição da oferta de emprego

Job Description

This role is for a ASIC design Lead for deep submicron technology with strong experience in end-to-end ASIC development, microarchitecture definition, RTL design, and technical leadership. The role requires ownership of a major ASIC/function from requirements analysis through implementation, verification, and silicon qualification. Experience with low-power ASIC design techniques and clock domain crossing

• Knowledge of AMS verification methodologies
• Exposure to silicon bring-up and lab validation
• Familiarity with EDA tools from Synopsys, Cadence, or Mentor

Job Description

This role is for a ASIC design Lead for deep submicron technology with strong experience in end-to-end ASIC development, microarchitecture definition, RTL design, and technical leadership. The role requires ownership of a major ASIC/function from requirements analysis through implementation, verification, and silicon qualification. Experience with low-power ASIC design techniques and clock domain crossing

• Knowledge of AMS verification methodologies
• Exposure to silicon bring-up and lab validation
• Familiarity with EDA tools from Synopsys, Cadence, or Mentor

How You Will Contribute And What You Will Learn

• Ability to interpret and map documents from standard bodies to requirements/functions
• Work with the architecture and other cross functional teams like SDK, verification, emulation teams.
• Ability to comprehend high level requirements and create a microarchitecture document
• Provide technical leadership to a team of designers and be responsible for delivery by taking it through planning, definition and implementation phase.
• Handson experience with various aspects of ASIC design including RTL coding and design checks including lint, CDC, RDC, synthesis
• Strong design skills - should be able to review the arch, requirements and micro-arch, synthesis and timing reports.
• Work with verification and lab validation teams to debug and qualify the implementation.

Key Skills And Experience

• Candidate must have a bachelor's degree or higher in CS or EE with very good academics. Master's degree preferred
• 10+ years of experience and hands-on experience in delivery of a major function/ASIC
• Preferred: Prior experience in Ethernet/Networking domain
• Ability to mentor and bring together engineers with differing but valid technical viewpoints