ASIC Micro Architecture - Principal Engineer

Cyient Semiconductors; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading technology firm in Hyderabad is seeking an experienced ASIC Micro-Architecture Principal Engineer to define and deliver high-performance micro-architectures for complex ASICs and SoCs. The ideal candidate will have over 10 years of experience in micro-architecture development and a strong background in RTL coding using Verilog or SystemVerilog. This role involves significant cross-functional collaboration, requiring excellent communication and problem-solving skills. An educational background in Electrical or Computer Engineering is essential.

Qualifications

• 10+ years of experience in micro-architecture development for ASICs or SoCs.
• Successful micro-architecture projects from Definition to Tape-Out to Mass production.
• Strong proficiency in Verilog and SystemVerilog.

Responsibilities

• Define micro-architecture specifications and detailed design requirements.
• Analyze PPA trade-offs and optimize for performance, power, and area.
• Collaborate with cross-functional teams to ensure effective project execution.
• Create and maintain detailed documentation of micro-architecture specifications.

Skills

Micro-architecture development

RTL coding in Verilog/SystemVerilog

Problem-solving skills

Communication skills

Technical leadership

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

EDA tools (Synopsys, Cadence)

Scripting languages (Python, Perl, Tcl)

Job description

ASIC Micro-Architecture Principal Engineer

The ASIC Micro-Architecture Principal Engineer is responsible for defining, implementing, and delivering high-performance, power-efficient, and area-optimized micro-architectures for complex ASICs and SoCs. The role requires deep technical expertise across micro-architecture definition, RTL implementation, PPA optimization, and cross-functional execution from concept through tape-out and mass production.

Key responsibilities

• Define micro-architecture specifications: Translate high-level architectural requirements into detailed micro-architectural and functional specifications. This includes defining data paths, control logic, and pipeline stages.
• Performance, power, and area (PPA) trade-offs: Analyze and evaluate different design approaches to achieve optimal PPA metrics. Good in analysing downstream impact on PPA critical constraints.
• RTL development: Implement the micro-architecture in a hardware description language (HDL) like Verilog or SystemVerilog, with a focus on code quality, design structure, and integration.
• Cross-functional collaboration: Work closely with other engineering teams, including system architects, verification engineers, and physical design engineers, to ensure smooth project execution.
• Verification support:
• Timing closure and integration: Collaborate with the physical design team to ensure timing closure and resolve integration issues during the place-and-route phase.
• Documentation: Create and maintain comprehensive documentation, including micro-architecture specifications and design notes.

Required skills and qualifications

• Minimum 10+ years of proven experience in micro-architecture development for complex ASICs or Systems-on-a-Chip (SoCs), including elements like pipelining, caching, memory subsystems etc.
• Minimum 2 successful micro-architecture story from Definition to Tape-Out to Mass production.

RTL coding

Strong proficiency in hardware description languages such as Verilog and SystemVerilog.

ASIC design flow

A solid understanding of the full ASIC development flow, from design concept to tape-out.

Advanced knowledge

Expertise in specific micro-architectural concepts, such as bus architectures (AMBA or In-house), interconnects, and low-power design techniques (e.g., clock/power gating).

Tools and methodologies

• EDA tools: Familiarity with Electronic Design Automation (EDA) tools from vendors like Synopsys or Cadence.
• Scripting: Strong scripting skills using languages like Python, Perl, or Tcl for automation and flow development.
• Verification techniques (Optional): Knowledge of verification methodologies, including formal verification and static timing analysis.
• Problem-solving: Excellent analytical and problem-solving skills with a keen attention to detail.
• Communication: Strong verbal and written communication skills for effective cross-functional collaboration.
• Leadership: Demonstrated ability to provide technical leadership and mentor junior engineers.

Education

A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.