ASIC RTL Design Lead

eInfochips (An Arrow Company); Dadri; On-site; INR 2,800,000 - 6,000,000; Full time

Job summary

eInfochips (An Arrow Company) in Noida, India is seeking a highly skilled ASIC Design Lead (Senior & Mid-Level) to drive architecture definition, RTL development, and implementation for advanced SoC programs. You will collaborate with architecture, verification, and physical design teams to deliver production-quality silicon from specification through tape-out.

The role requires 6+ years of digital ASIC/SoC design, hands-on experience in synthesis, timing analysis, CDC, and low-power design

Qualifications

• 6+ years of experience in digital ASIC/SoC design.
• Hands-on experience in ASIC synthesis, timing analysis, and CDC methodologies.
• Working knowledge of P&R flows and low-power design using UPF.
• Deep understanding of end-to-end digital design and implementation flow.

Responsibilities

• Define and drive digital design architecture for complex SoC and ASIC subsystems
• Translate micro-architecture specifications into scalable and high-quality RTL implementations
• Refine functional requirements throughout the design lifecycle in collaboration with cross-functional teams
• Implement low-power design methodologies aligned with system-level goals
• Perform synthesis, timing closure, and design optimization
• Drive design quality through CDC analysis, constraint development, and sign-off readiness
• Partner with verification and physical design teams to ensure successful integration and tape-out

Skills

ASIC design

RTL development

Synthesis

Timing analysis

CDC methodologies

UPF low-power design

End-to-end design flow

Education

Bachelor's or Master's in Electrical/Electronics

Tools

UPF

Job description

ASIC Design Lead (Senior & Mid-Level) | ASIC / SoC Development

Location: Noida, India

Experience: 6+ Years

Employment Type: Full-Time

About the Role

We are seeking highly motivated ASIC Design Leads to contribute to next-generation silicon development programs. In this role, you will work across architecture definition, RTL development, and implementation, enabling high-performance and power-efficient ASIC/SoC designs.

You will collaborate closely with architecture, verification, and physical design teams to deliver production-quality silicon from specification through tape-out.

Responsibilities

• Define and drive digital design architecture for complex SoC and ASIC subsystems
• Translate micro-architecture specifications into scalable and high-quality RTL implementations
• Refine functional requirements throughout the design lifecycle in collaboration with cross-functional teams
• Implement low-power design methodologies aligned with system-level goals
• Perform synthesis, timing closure, and design optimization
• Drive design quality through CDC analysis, constraint development, and sign-off readiness
• Partner with verification and physical design teams to ensure successful integration and tape-out

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or related discipline
• 6+ years of experience in digital ASIC/SoC design
• Hands-on experience in ASIC synthesis, timing analysis, and CDC methodologies
• Working knowledge of P&R flows and low-power design using UPF
• Deep understanding of end-to-end digital design and implementation flow

Preferred Qualifications

• Experience owning complex IP or subsystem delivery
• Exposure to advanced node designs and power optimization techniques
• Strong debugging and design closure experience across multiple tape-outs

Why Join Us

• Work on cutting-edge semiconductor technologies and complex silicon programs
• Collaborate with globally distributed engineering teams
• Opportunity to influence architecture and product innovation
• Culture focused on technical excellence, ownership, and continuous learning