Physical Verification Engineers

Digicomm Semiconductor INC; Pune District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Digicomm Semiconductor INC in Pune invites a layout verification engineer to join our semiconductor design team. The role focuses on DRC, LVS, ERC, DFM, and RET to ensure manufacturability and electrical correctness of complex IC layouts.

You will collaborate with design, process, and manufacturing teams, perform calibration of extraction tools for the chosen process, and document verification methodologies and results to support yield and reliability.

Responsibilities

• Design Rule Checking (DRC): Run DRC checks with industry tools to identify manufacturing rule violations.
• Layout vs. Schematic (LVS) Verification: Ensure physical layout matches schematic and resolves connectivity discrepancies.
• Electrical Rule Checking (ERC): Verify layout meets electrical constraints to ensure correct IC operation.
• Design for Manufacturing (DFM): Collaborate with design/manufacturing teams to optimize layout for fabrication.
• Process Technology Calibration: Calibrate layout extraction tools to match fabrication process technology.
• Resolution Enhancement Techniques (RET): Implement RET to improve printability of layouts during lithography.
• Fill Insertion: Insert fill cells to improve planarity and reduce wafer warping.
• Multi-Patterning and Advanced Nodes: Address multi-patterning and metal variation challenges.
• Hotspot Analysis: Identify hotspot areas and address potential defects or yield issues.
• Post-Processing Simulation: Run simulations to ensure layout is compatible with manufacturing and does not introduce parasitics.
• Process Integration Checks: Coordinate with process teams to ensure smooth integration of design with fabrication process.
• Documentation: Maintain detailed documentation of verification processes, methodologies, and results.

Job description

• Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues.
• Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies.
• Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended.
• Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns.
• Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication.
• Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process.
• Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress.
• Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations.
• Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues.
• Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics.
• Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process.
• Documentation: Maintain detailed documentation of verification processes, methodologies, and results.