Physical Verification Engineer

LeadSoc Technologies; Dadri, Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

LeadSoc Technologies is seeking a seasoned physical verification engineer in India to verify semiconductor devices with LVS, DRC, Innovus, and Caliber. The role requires close collaboration with design teams to address layout, routing, and signal integrity challenges, and to document verification results and improvement recommendations.

The candidate will contribute to root cause analyses of failures observed during production testing and support process improvements across SoC projects.

Qualifications

• 3–8 years of experience in physical verification engineering or a related field.
• Strong understanding of semiconductor manufacturing processes and industry standards.
• Proficiency with LVS, DRC, Innovus, or Caliber for physical verification.
• Experience with complex SoC designs and multi-layer interconnects.

Responsibilities

• Perform physical verification of semiconductor devices using LVS, DRC, Innovus, Caliber.
• Collaborate with design engineers to resolve layout, routing, and signal integrity issues.
• Develop and maintain documentation of verification results and recommendations.
• Participate in root cause analysis of failures during production testing.

Skills

Physical verification

Root cause analysis

Documentation

Cross-functional collaboration

Tools

LVS

DRC

Innovus

Caliber

Job description

Roles and Responsibilities :

• Perform physical verification of semiconductor devices using various tools such as LVS, DRC, Innovus, Caliber.
• Collaborate with design engineers to identify and resolve issues related to device layout, routing, and signal integrity.
• Develop and maintain documentation for physical verification results and recommendations for improvement.
• Participate in root cause analysis of failures during production testing.

Job Requirements :

• 3-8 years of experience in physical verification engineering or a related field.
• Strong understanding of semiconductor manufacturing process flow and relevant industry standards (e.g., ITRS).
• Proficiency in one or more EDA tools used for physical verification (LVS, DRC, Innovus, Caliber).
• Experience working on complex SoC designs with multiple layers of interconnects.