Senior Physical Design Engineer

Verifast Technologies; Ahmedabad District; On-site; INR 1,300,000 - 2,100,000; Full time

Job summary

VeriFast Technologies is seeking an experienced Physical Design Engineer with 7+ years of hands-on ASIC/SoC PD experience for RTL-to-GDS flows. Located in Ahmedabad, Gujarat, you will own blocks through complete flows, including floorplanning, CTS, routing, and signoff.

The role emphasizes strong debugging, collaboration with cross-functional teams, and familiarity with advanced nodes (TSMC 7nm/5nm/3nm). Mentoring junior engineers is also expected.

Qualifications

• 7+ years of hands-on ASIC/SoC physical design experience.
• Experience with advanced nodes such as TSMC 7nm/5nm/3nm.
• Proven tapeouts on advanced nodes preferred.
• Strong debugging and cross-functional collaboration skills.

Responsibilities

• Own blocks through RTL-to-GDS physical implementation flow.
• Perform floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.
• Drive timing closure, STA, ECO implementation, power, area optimization.
• Signoff: DRC, LVS, ANT, and EMIR.
• Analyze implementation challenges and provide RTL and routability feedback.
• Identify risks and recommend design changes to avoid schedule issues.
• Support block integration and full-chip assembly.
• Collaborate with STA, Power Integrity, DFT, Physical Verification, RTL, Architecture, and Signoff teams.
• Debug and resolve timing, congestion, clocking, power, routing, and physical design issues.
• Contribute to improving physical design methodologies and flows.
• Mentor junior engineers while remaining hands-on.

Skills

RTL-to-GDS flows

Floorplanning

Synthesis

Placement

CTS

Routing

STA

Timing closure

Power optimization

DRC/LVS/ANT/EMIR

Education

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI

Tools

Synopsys EDA tools

Cadence EDA tools

Siemens EDA tools

RTL-to-GDS flow platforms

Job description

Job Title: Physical Design Engineer (7+ Years)

Location: Ahmedabad, Gujarat

Company: VeriFast Technologies

About the Role

VeriFast Technologies is looking for an experienced Physical Design Engineer with 7+ years of hands-on experience in ASIC/SoC physical implementation and RTL-to-GDS (RT2GDS) flows.

The ideal candidate should have strong expertise in advanced technology nodes, physical implementation, timing closure, power optimization, and physical signoff. Candidates with 3+ successful tapeouts on advanced nodes such as TSMC 7nm, 5nm, or 3nm will be highly preferred.

Key Responsibilities

• Own complex ASIC/SoC blocks through the complete RTL-to-GDS physical implementation flow.
• Perform block-level floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.
• Drive timing closure, STA, ECO implementation, power, area, congestion, and routability optimization.
• Perform and drive closure of DRC, LVS, ANT, and other physical verification signoff activities.
• Perform EM/IR (EMIR) analysis and drive issues to closure.
• Analyze implementation challenges and provide RTL and routability feedback to full-chip design stakeholders.
• Identify physical implementation risks proactively and recommend design changes to avoid schedule-critical closure issues.
• Support block integration, hierarchical implementation, and full-chip assembly.
• Collaborate with STA, Power Integrity, DFT, Physical Verification, RTL, Architecture, and Signoff teams.
• Debug and resolve complex timing, congestion, clocking, power, routing, and physical design issues.
• Contribute to improving physical design methodologies, flows, and implementation quality.
• Mentor junior engineers while remaining highly hands-on with physical implementation activities.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• 7+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong experience in RTL-to-GDS / RTL-to-GDSII physical implementation flows.
• Hands-on experience with advanced technology nodes, preferably TSMC 7nm / 5nm / 3nm.
• Experience with at least 3 successful tapeouts is highly preferred.
• Strong understanding of:

• Floorplanning
• Power planning
• Synthesis
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical optimization
• ECO implementation
• Static Timing Analysis (STA)
• Timing closure
• Power and area optimization
• Congestion and routability analysis

• Hands-on experience with DRC, LVS, Antenna (ANT), EMIR, and physical signoff.
• Strong debugging and problem-solving skills.
• Good communication and cross-functional collaboration skills.

Preferred Skills

• Experience working on complex ASIC/SoC designs and hierarchical implementation.
• Strong understanding of full-chip physical design and block-level implementation.
• Experience with advanced-node physical design challenges.
• Ability to analyze timing, congestion, power, routing, and physical verification issues and drive them to closure.
• Experience working with industry-standard EDA tools from Synopsys, Cadence, or Siemens EDA.
• Experience mentoring engineers and contributing to physical design flow/methodology improvements.