ASIC Physical Design Lead

Sevya Multimedia; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Sevya Multimedia seeks an ASIC Physical Design Lead to drive complex projects from Netlist to GDSII, focusing on timing closure and full-chip design. You will work closely with packaging teams to integrate pads logs, bump placement, and RDL routing.

The role requires mentoring junior engineers and advancing design methodologies. Applicants should bring 10+ years in ASIC physical design, strong leadership, and proficiency with industry-standard EDA tools and multi-voltage, multi-clock domain

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 10 years of experience in ASIC physical design.
• Expertise in industry-standard EDA tools for physical design and verification.
• Strong understanding of timing closure techniques and challenges.
• Experience with full-chip design and multi-voltage/multi-clock domain designs.
• Excellent problem-solving and analytical skills.
• Strong communication and leadership abilities.

Responsibilities

• Lead the physical design of complex ASIC projects from Netlist to GDSII.
• Perform timing closure tasks including synthesis, place and route, and static timing analysis.
• Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.
• Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing.
• Mentor junior engineers and guide them on physical design methodologies.
• Drive innovation and efficiency in physical design workflows.

Skills

Timing closure

Full-chip design

EDA tools

Leadership

Mentoring

Problem solving

Communication

Education

Bachelor’s or Master’s in EE/CE

Tools

Industry-standard EDA tools

Job description

As ASIC Physical Design Lead y ou will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients.

Job Summary:

We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing.

Key Responsibilities:

• Lead the physical design of complex ASIC projects from Netlist to GDSII.
• Perform timing closure tasks including synthesis, place and route, and static timing analysis.
• Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.
• Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing.
• Mentor junior engineers and guide them on physical design methodologies.
• Drive innovation and efficiency in physical design workflows.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 10 years of experience in ASIC physical design.
• Expertise in industry-standard EDA tools for physical design and verification.
• Strong understanding of timing closure techniques and challenges.
• Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs.
• Excellent problem-solving and analytical skills.
• Strong communication and leadership abilities.