Physical Design Lead

Spot Your Leaders & Consulting; Bengaluru; On-site; INR 3,500,000 - 7,500,000; Full time

Job summary

Spot Your Leaders & Consulting seeks a Senior Physical Design Lead with 14+ years of ASIC/VLSI experience to own end-to-end physical implementation from RTL to GDSII for high-frequency SoCs. You will drive timing closure, CTS, power convergence, and sign-off across core platforms and complex designs while collaborating with ASIC vendors and cross-functional teams.

The ideal candidate will have hands-on RTL-to-GDSII flow expertise, strong leadership, and a track record of delivering full-chip

Qualifications

• Minimum 14+ years in ASIC/VLSI physical design.
• Hands-on RTL-to-GDSII physical implementation experience.
• Strong expertise in CTS, timing analysis and ECOs.
• Experience with 1 GHz+ high-frequency designs.
• Experience collaborating with ASIC vendors and cross-functional teams.

Responsibilities

• Lead full-chip physical design and implementation from RTL to GDSII.
• Drive timing closure through physical synthesis, PnR, and ECOs.
• Own end-to-end front-end to back-end implementation flow.
• Perform RTL synthesis, floorplanning, placement, routing, and CTS.
• Manage timing constraints, timing analysis and optimization.
• Lead sign-off for physical and timing; support critical-path SPICE.
• Drive IO planning and interface timing; optimize PPA.
• Collaborate with Systems, Architecture and Design teams.
• Provide technical leadership on methodologies and automation.
• Coordinate with ASIC vendors to meet schedule and sign-off targets.

Skills

Leadership

RTL-to-GDSII flow

Physical design

Clock Tree Synthesis

Timing closure

ECO implementation

Power optimization

VLSI/ASIC

1 GHz+ designs

Vendor collaboration

Tools

Place & Route tools

FV/Timing tools

Job description

Level: Senior Leadership / Technical Lead

Job Description:

We are looking for an experienced Physical Design Lead with a minimum of 14+ years of expertise in ASIC/VLSI physical design and a strong full-chip implementation background. The role will be responsible for driving physical implementation, timing closure, power convergence, and sign-off of complex, high-frequency and low-power SoCs.

The ideal candidate should have strong hands-on experience across the complete RTL-to-GDSII flow, including synthesis, floor planning, physical synthesis, placement, CTS, routing, timing analysis, ECO implementation, and physical design closure. Experience working with ASIC vendors and cross-functional Systems, Architecture, Application and Design teams is essential.

Key Responsibilities

• Lead full-chip physical design and implementation of complex ASIC/SoC designs from RTL to GDSII.
• Drive timing closure through physical synthesis, Place & Route, timing optimization and ECO implementation.
• Own and drive the complete front-end to back-end implementation flow, including:
• RTL synthesis
• Formal verification (FV)
• Floorplanning
• Placement and routing
• Timing constraints
• Timing analysis and optimization
• ECO implementation
• Physical and timing sign-off
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Drive physical design and timing convergence at block, cluster and full-chip levels.
• Lead physical design closure for large and complex designs operating at 1 GHz+ frequencies.
• Own Clock Tree Synthesis (CTS) and clock distribution for high-frequency designs.
• Work closely with Systems and Application teams to develop timing-closure-friendly SoC architectures and IO interfaces.
• Drive IO planning and IO pin optimization in alignment with overall chip architecture and timing requirements.
• Define and streamline timing sign-off criteria, timing analysis methodologies and implementation flows.
• Develop and enhance automation scripts for timing closure and automatic ECO generation.
• Support critical-path analysis, including SPICE-based simulation and analysis where required.
• Drive physical implementation and timing convergence for high-frequency, low-power CPU, GPU and/or ASIC designs.
• Collaborate with ASIC vendors and internal design teams to resolve implementation challenges and achieve schedule, PPA and sign-off targets.
• Identify physical design bottlenecks and drive optimization across performance, power and area (PPA).
• Provide technical leadership and guidance on physical design methodologies, flows and best practices.

Required Skills & Experience

• 14+ years of relevant experience in ASIC/VLSI Physical Design.
• Strong hands-on experience with the RTL-to-GDSII physical implementation flow.
• Strong expertise in:
• Physical synthesis
• Floorplanning
• Placement & Routing
• Clock Tree Synthesis (CTS)
• Timing analysis and closure
• Timing constraints
• ECO implementation
• Power optimization and convergence
• Experience with 1 GHz+ high-frequency designs is highly desirable.
• Strong experience in full-chip timing closure for complex SoCs.
• Experience with CPU, GPU and/or complex ASIC/SoC designs, preferably in high-performance and low-power environments.
• Strong understanding of clock distribution, CTS and clock optimization.
• Experience working with ASIC vendors and external implementation teams.
• Strong understanding of timing sign-off methodologies and timing analysis flows.
• Experience developing or enhancing automation scripts for timing closure / ECO generation.
• Exposure to critical-path SPICE simulation and analysis.
• Strong understanding of PPA optimization and design trade-offs.
• Ability to work closely with Architecture, Systems, RTL, Design, Verification and Application teams.

Preferred Technical Expertise

• Experience with industry-standard Physical Design / Place & Route tools.
• Strong understanding of advanced-node physical design challenges.
• Experience with high-performance, low-power SoC implementation.
• Experience handling complex timing scenarios and multi-corner/multi-mode timing closure.

*Full-chip experience is mandatory; candidates with only block-level physical design experience would not be suitable for this role.