Static Timing Analysis Engineer

Intel; Bengaluru; Hybrid; INR 1,200,000 - 1,800,000; Full time

Job summary

Intel is seeking a Physical Design Timing Engineer in Bengaluru, India. This role focuses on ensuring optimal performance of next-generation SoCs, developing high-quality timing models and collaborating with cross-functional teams.

The ideal candidate will have at least 8 years of experience in Physical Design, a Bachelor's degree in Electrical Engineering, and proficiency in static timing analysis. Intel offers a hybrid work model allowing for flexible onsite and remote work.

Qualifications

• 8+ years of experience in Physical Design with a Bachelor's degree, or 6+ years with a Master's degree.
• Proficiency in static timing analysis tools and methodologies.
• Demonstrated expertise in timing modeling and verification.

Responsibilities

• Perform timing analysis and optimization for design functionality and performance.
• Generate and verify timing constraints, resolving timing violations.
• Collaborate with teams to achieve clocking balance and power delivery optimization.

Skills

Static timing analysis

Timing modeling

Optimization techniques

Collaboration skills

Education

Bachelor's degree in Electrical Engineering or related field

Job description

Overview

The Role and Impact: As a Physical Design Timing Engineer, you will play a pivotal role in advancing Intel's next-generation SoCs by ensuring their optimal performance and efficiency. Your expertise will directly impact the success of Intel's products, enabling innovation across high-performance computing, AI, and beyond. You will work on cutting-edge designs, collaborating with cross-functional teams to tackle complex challenges while delivering high-quality timing models that empower the physical design team to excel. This is an exciting opportunity to contribute to Intel's mission of shaping the future of technology.

Responsibilities

• Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels.
• Generate and verify timing constraints, addressing and resolving timing violations during SoC development.
• Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines.
• Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process.
• Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions.
• Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance, power delivery optimization, and efficient partitioning.
• Partner closely with the clocking team to refine methodologies and validate integration flows for chip-level timing solutions.

Qualifications

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years with a Master’s degree, or 4+ years with a PhD.
• Proficiency in static timing analysis tools and methodologies.
• Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques.
• Technical understanding of PVT conditions and their application in timing analysis.

Preferred Qualifications:

• Advanced knowledge of SoC development, clocking design principles, and timing methodologies.
• Strong collaboration skills, with a proven ability to work across architecture, logic design, and physical design teams.
• Experience in high-performance computing or low-power design environments.
• Commitment to continuous learning and staying updated on industry advancements.

Job Details

Job Type: Experienced Hire

Shift: Shift 1 (India)

Location: India, Bangalore

Organization

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

EEO and Work Model

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.