ASIC Physical Design Engineer

Vicharak; Surat; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Vicharak is redefining high-performance computing by expanding from FPGA to custom silicon. We are seeking an ASIC Physical Design Engineer to own floorplanning, power grid design, CTS, and routing for our acceleration chips.

You will analyze Standard Cell libraries, perform parasitic extraction, and work with the systems team to define chip architecture, feasibility, and area/power estimates. You will conduct STA, DRC/LVS, and reliability analyses, and implement DFT structures for silicon

Qualifications

• Proven track record in RTL-to-GDSII flows, including logic synthesis and place-and-route (PnR).
• Strong understanding of ASIC physical design concepts (floorplanning, CTS, routing).
• Experience with timing closure and multi-corner designs; scripting in Tcl/Python for automation.

Responsibilities

• Own the physical design process: floorplanning, power grid design, CTS, and routing for custom acceleration chips.
• Analyze Standard Cell libraries and macros; assess transistor-level performance and parasitic extraction (RC modeling).
• Collaborate with systems team to define chip architecture, feasibility studies, and area/power estimates.
• Perform STA, DRC/LVS, and reliability analyses; implement Design-for-Test (DFT) structures and assist in silicon bring-up.

Skills

RTL-to-GDSII

PnR

Timing closure

Floorplanning

CTS

Synthesis

EDA tools

Tcl/Python

Tools

Cadence

Synopsys

Mentor Graphics

Job description

At Vicharak, we are redefining the limits of high-performance computing. While our roots are deeply embedded in innovative FPGA technology with our VAAMAN platform, we are expanding our horizons toward custom silicon to achieve unparalleled efficiency. We are looking for an ASIC Physical Design Engineer .

What You Will Learn:

Master the transition from RTL to GDSII, understanding the intricacies of synthesis, floorplanning, and routing.

Gain a deep understanding of FinFET/GAAFET structures, short-channel effects, and how layout choices impact device-level reliability.

Learn how to balance the "PPA triangle" (Power, Performance, and Area) to meet the demanding requirements of accelerator hardware.

Utilize industry-standard EDA tools (Cadence, Synopsys, or Mentor Graphics) for physical implementation and sign-off.

Understand how physical constraints in silicon dictate the performance of high-level software and compilers.

What You Will Work On:

You will take ownership of the physical design process, including floorplanning, power grid design, clock tree synthesis (CTS), and routing for our custom acceleration chips.

Analyze Standard Cell libraries and custom macros, focusing on transistor-level performance, leakage current, and parasitic extraction (RC modeling).

Work closely with the systems team to define chip architecture, performing feasibility studies and area/power estimations.

Conduct rigorous Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability Analysis (Electromigration and Thermal modeling).

Implement Design-for-Test (DFT) structures and collaborate with the hardware team to bring up and debug silicon post-fabrication.

Preferred Skills:

Proven track record in RTL-to-GDSII flows, including logic synthesis and place-and-route (PnR).

Strong understanding of semiconductor physics, including CMOS fabrication processes and device-level reliability (HCI, NBTI).

Expertise in timing closure for multi-corner, multi-mode designs and deep understanding of constraints (SDC).

Strong skills in Tcl, Python, or Perl to automate complex EDA workflows.

Ability to translate high-level system requirements into efficient physical floorplans and hierarchies.

A "perfection seeker" mentality with the discipline to handle the high stakes of custom silicon tape‑outs.

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