Fullchip PD Implementation Lead

Eximietas Design LLC; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

Eximietas Design LLC in Bangalore seeks an experienced Fullchip PD Implementation Lead to drive cutting-edge physical design flows for complex ASICs. You will coordinate with RTL, DFT and cross-functional teams to ensure timely delivery of high-quality designs.

The role requires 10+ years in ASIC physical design, strong command of Synthesis, PnR and Signoff tools, and leadership to mentor a PD team. Expect challenging targets and close collaboration with multiple design groups for successful

Qualifications

• Bachelor's or Master's in Electrical Engineering or Electronics/Communications.
• 10+ years' experience in physical design of ASICs.
• Proficient in Synthesis, PnR, Signoff with Cadence, Synopsys and Mentor.
• Strong scripting in TCL or Python for automation and tool customization.

Responsibilities

• Lead full chip implementation with partitioning, GPIO, PLL, Serdes placement and area allocation.
• Perform synthesis, floorplanning, placement, clock routing and PPA optimization for high-speed ASICs.
• Define physical design strategies to meet performance, power and area targets.
• Plan clocking and distribution across the grid using Mesh/CTS techniques.
• Oversee bump planning, RDL routes for PG and signal, and package-level SoC integration.
• Drive timing, power and area analyses, and optimize QoR with design tweaks.
• Provide technical leadership and mentor junior engineers in PD flows.
• Collaborate with RTL and DFT teams to meet tap-out constraints.

Skills

Physical design

ASICs

Leadership

Scripting

EDA tools

Education

Bachelors/Master's in EE/EC

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Job Title: Fullchip PD Implementation Lead

Location: Bangalore

Experience: 10+ years

Job Overview: We are seeking an exceptional Fullchip PD Implementation Lead to take a key role in our semiconductor design team. As a Fullchip PD Implementation Lead , you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs.

Responsibilities:

• Perform full chip implementation with partition, GPIO, PLL, Serdes placement, area allocation to partitions.
• Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.
• Define and drive physical design strategies to meet aggressive performance, power, and area targets.
• Perform efficient Clock planning and distribution to entire grid with the use of Mesh or CTS
• Do Bump planning & placement, RDL routes for PG and Signal
• Work on Package level with complete SoC integration.
• Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR.
• Fullchip signoff closure support for STA, PV, LEC, IR/EM, CLP very efficiently.
• Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence.
• Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs.
• Support and Development of advanced physical design methodologies and flows for complex semiconductor designs.

Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications.
• 10+ years of experience in physical design of ASICs
• Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure.
• Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
• Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
• Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
• Proven ability to lead and mentor junior engineers, fostering their professional growth and development.

Preferred qualifications:

• Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
• Has at least worked on 2 full chip implementation of large size silicon.
• Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues.
• Experience in handling Partitions and blocks for size estimation, pin assignment, CTS.
• Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration.
• Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
• Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF.
• Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks.
• Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.
• Experience and good understanding in various foundries and their Backend implementation requirement.