Physical Design Engineer

NXP Semiconductors; Maharashtra; Sur place; INR 1 400 000 - 2 100 000; Plein temps

Résumé du poste

NXP Semiconductors is seeking a Physical Design Engineer (G2) to join our growing VLSI team in India, focusing on implementation and signoff of complex SoC/IP blocks in advanced technology nodes.

You will collaborate with RTL and DFT teams, drive timing convergence, routing, and signoff while upholding PPA and reliability standards. Flexible scripting will aid workflow improvements and automation.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering or Microelectronics.
• 3–5 years of ASIC Physical Design experience.
• Strong understanding of physical design flow (FP → P&R → Signoff) and STA fundamentals.
• Experience with industry EDA tools: Cadence or Synopsys suite.
• Scripting skills in Tcl, Python or Shell.
• Experience in 16nm and below nodes; knowledge of UPF/CPF low-power flows.
• Familiarity with Calibre for physical verification.

Responsabilités

• Execute block-level physical design from synthesized netlist to GDSII: floorplanning and power grid design.
• Placement and optimization, clock tree synthesis, routing and post-route optimization.
• Drive timing convergence across MCMM scenarios and ensure design closure (setup/hold).
• DRC/LVS clean signoff, IR drop and electromigration compliance.
• Debug and resolve congestion, SI/crosstalk issues and ECOs.
• Collaborate with RTL, DFT, packaging and full-chip teams.
• Contribute to design methodologies and automation through scripting.
• Follow and enforce NXP design methodologies, quality and reliability standards.

Connaissances

ASIC Physical Design

Static Timing Analysis

CMOS Digital Design

Scripting (Tcl/Python/Shell)

EDA Tools Experience

Floorplanning

Power Integrity/IR Drop

CTS/Routing

Formation

Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics

Outils

Cadence Innovus/Genus

Synopsys ICC2/Fusion Compiler

PrimeTime

Calibre

Description du poste

Job Summary

NXP Semiconductors is seeking a Physical Design Engineer (G2) with strong fundamentals in physical design implementation to join our growing VLSI team. In this role, you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes, ensuring high-quality delivery aligned with NXP’s stringent PPA (Power, Performance, Area) and reliability standards.

Key Responsibilities

• Execute block-level physical design from synthesized netlist to GDSII:
  • Floorplanning and power grid design
  • Placement and optimization
  • Clock Tree Synthesis (CTS)
  • Routing and post-route optimization
• Drive timing convergence across MCMM scenarios in collaboration with STA teams
• Ensure design closure including:
  • Setup/hold timing closure
  • DRC/LVS clean signoff
  • IR drop and electromigration (EM) compliance
• Debug and resolve:
  • Congestion issues
  • SI/crosstalk problems
  • Functional and physical ECOs
• Collaborate cross-functionally with:
  • RTL/design teams to improve QoR
  • DFT teams for test readiness
  • Packaging and full-chip integration teams
• Contribute to methodology improvements and automation through scripting
• Follow and enforce NXP design methodologies, quality and reliability standards

Required Qualifications

• Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics
• 3–5 years of experience in ASIC Physical Design
• Strong understanding of:
  • Physical design flow (FP → P&R → Signoff)
  • Static Timing Analysis fundamentals
  • CMOS digital design basics
• Hands-on experience with industry EDA tools:
  • Cadence (Innovus/Genus) or Synopsys (ICC2/Fusion Compiler, PrimeTime)
• Good scripting skills in Tcl, Python, or Shell
• Experience in advanced nodes (16nm and below)
• Knowledge of:
  • Low-power design flows (UPF/CPF)
  • Multi-voltage / multi-domain designs
• Familiarity with physical verification tools (Calibre)