Lead Physical Design Engineer

Cadence System Design and Analysis; Bengaluru; On-site; INR 80,000 - 150,000; Full time

Job summary

An established industry player is seeking a talented individual to join their Senior Leadership Team in Design Verification. This exciting opportunity involves leading larger projects in the semiconductor manufacturing sector, focusing on challenging DDR PHY IP and Testchip Physical Design for tech nodes below 7nm. The ideal candidate will have a strong background in Netlist-GDS physical design, scripting in TCL and Python, and experience with Cadence tools. Join a dynamic team where innovation and excellence are at the forefront of technology development, and make a significant impact in the field.

Qualifications

• 3+ years of experience in Netlist-GDS physical design.
• Hands-on scripting experience in TCL & Python.

Responsibilities

• Ownership of physical design blocks including floorplanning and PNR.
• Contribute to design methodology and flow automation.

Skills

Netlist-GDS physical design

CTS and custom clocking

STA

PV

Scripting in TCL

Scripting in Python

Education

Bachelor's degree in Electronics

BE / BTech

Tools

Cadence Innovus

Cadence Genus

Cadence Tempus

Cadence Voltus

Job description

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Looking for Senior Leadership Team in Design Verification, DFT, PD — I have an exciting opportunity for those ready to lead larger projects.

Qualifications: BE / BTech

Experience: 3-7 years

Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.

1. Take ownership of one or more physical design blocks, including floorplanning, CTS, PNR, QRC, STA, PV & IR.
2. Contribute to design methodology and flow automation.
3. Innovate and implement Power, Performance, and Area optimization techniques.
4. Participate in IP release to customers and support team in standardization & documentation of learnings.

Key Skills:

• Netlist-GDS physical design, 7nm+ technology nodes
• CTS and custom clocking, STA, PV
• Scripting in TCL & Python

Minimum Qualifications:

• Bachelor’s degree in Electronics or equivalent practical experience
• 3+ years of experience with in-depth knowledge of Netlist-GDS physical design
• Experience with sub-7nm tech nodes
• Hands-on scripting experience in TCL & Python

Preferred Qualifications:

• Experience in hardening DDR PHY designs
• Experience in physical synthesis and constraints design
• Proficiency with Cadence tools: Innovus, Genus, Tempus & Voltus
• Experience in RDL routing, PERC ESD checks
• Knowledge of lower tech nodes like N3, Samsung N5, N4 is a plus

Additional Details:

• Seniority level: Entry level
• Employment type: Full-time
• Industry: Semiconductor Manufacturing

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