Physical Design Engineer

Tanisha Systems; Bengaluru; On-site; INR 2,300,000 - 3,500,000; Full time

Job summary

Tanisha Systems in Bengaluru is seeking a senior ASIC Physical Design Engineer with 6+ years of hands-on experience in physical design and the complete backend flow (Synthesis, PnR, STA, physical verification, LEC and EMIR). The role requires proficiency with cutting-edge nodes (3nm/5nm) and ECOs for timing convergence, including Tweaker/PT ECOs.

You will work on complex designs with EDA tools such as Fusion Compiler, DC Compiler, ICC2, Formality, StarRC, and PrimeTime, and you should have

Qualifications

• 6+ years of experience in physical design
• Expertise in the entire backend design flow: Synthesis, PnR, STA, Physical verification, LEC and EMIR
• Expertise in latest technology nodes - 3nm, 5nm etc.
• Expertise in preparing complex ECOs for timing convergence through Tweaker / PT ECOs
• Expertise in Physical verification at partition, SS and FC levels
• Experience in Formal verification / Logic Equivalence checks
• Experience in low power design implementation including UPF, multi-voltage domains, and power gating
• Experience in EDA tools Fusion Compiler, EDI, DC Compiler, ICC2, Formality, Conformal LEC, Redhawk, StarRC and PrimeTime
• Experience in scripting languages PERL TCL & Shell scripting.

Skills

Physical design

Backend design flow

Synthesis

PnR

STA

Physical verification

LEC

EMIR

Eco timing convergence

Low power design

UPF

Power gating

Multi-voltage domains

Scripting: PERL

Scripting: TCL

Shell scripting

Tools

Fusion Compiler

EDI

DC Compiler

ICC2

Formality

Conformal LEC

Redhawk

StarRC

PrimeTime

Job description

• 6+ Years experience in physical design
• Expert knowledge of the entire backend design flow (Synthesis, PnR, STA, Physical verification, LEC and EMIR )
• Expertise in latest technology nodes - 3nm, 5nm etc.
• Expertise in preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / PT ECOs
• Expertise in Physical verification at partition level, SS level and FC level.
• Experience in Formal verification / Logic Equivalence checks
• Experience in low power design implementation including UPF, multi-voltage domains, and power gating.
• Experience in EDA tools Fusion Compiler, EDI, DC Compiler, ICC2, Formality, Conformal LEC, Redhawk, StarRC and Prime time.
• Experience in scripting languages PERL TCL & Shell scripting .

Prior experience on NVIDIA projects is must.

Role & responsibilities

Preferred candidate profile