Physical Design Engineer

Tata Consultancy Services; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

Tata Consultancy Services in Bengaluru is seeking an experienced IC Design Engineer to work on full-chip floor planning, PNR, IO planning, and routing tasks across 7nm/10nm nodes.

You will be involved in ECOs, synthesis, STA, power analysis, and physical verification with cross-functional teams. Strong hands-on experience across advanced nodes is essential.

Qualifications

• Must-Have - Hands on experience on Full chip floor plan, Full chip PNR, Design Partitioning
• Hands on experience on IO Planning, Bump Plan and RDL Routing
• Experience on ECOs, Synthesis and STA, Power analysis
• Hands on experience on Physical verification
• Hands on experience on 7nm and 10nm technology nodes

Responsibilities

• Hands on experience on IO Planning, Bump Plan and RDL Routing
• Experience on ECOs, Synthesis and STA, Power analysis
• Hands on experience on Physical verification

Skills

Full chip floorplan

Full chip PNR

IO Planning

Bump Plan

RDL Routing

ECOs

Synthesis

STA

Power analysis

Physical verification

7nm/10nm nodes

Job description

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes.

Must-Have - Hands on experience on Full chip floor plan, Full chip PNR, Design Partitioning

Hands on experience on IO Planning, Bump Plan and RDL Routing

Experience on ECOs, Synthesis and STA, Power analysis

Hands on experience on Physical verification

Hands on experience on 7nm and 10nm technology nodes

Good-to-Have Effective communication skills to interact with cross functional teams.