Physical Design Engineer

Innosilica; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Innosilica in Bengaluru, India, seeks a Physical Design Engineer with 3+ years of hands-on PnR experience to deliver high-performance SoC flows for sub-10nm mobile designs.

You will optimize floorplanning, placement, routing, CTS, timing, and ECOs, with a focus on PDN and clock-tree optimization. Proficiency in Perl/Python and TCL is required, with strong cross-functional collaboration.

Qualifications

• 3+ years hands-on experience in PnR steps (Floor planning, Power planning, Placement & Optimization, CTS, Routing, STA, ECO, DRC).
• Strong know-how of high frequency design and advanced tech nodes.
• In-depth PDN optimization and clock tree tuning experience.
• Experience with PnR tool knobs/recipes for PPA optimization.
• Automation experience with Perl/Python and TCL.

Responsibilities

• Deliver high-performance design flows for sub-10nm SoCs in the mobile space.
• Collaborate in cross-site cross-functional teams to optimize physical design.
• Drive DRC closure and timing closure through advanced PDN and CTS techniques.

Skills

Floor planning

Power planning

Placement & Optimization

CTS

Routing

Static timing analysis

Post route optimization

ECO implementation

DRC closure

Education

BTECH/MTECH in Electrical/Electronics/CS

Tools

Perl

Python

tcl

Job description

We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space.

Job Requirement:

• 3+ years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure.
• Well versed with high frequency design & advanced tech node implementation
• In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience.
• In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
• Well versed with tackling high placement density/congestion bottlenecks.
• In depth knowledge of PnR tool knobs/recipes for PPA optimization.
• Experience in automation using Perl/Python and tcl.
• Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Experience (years) :3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent