Physical Design Engineer

ACL Digital; Bengaluru; On-site; INR 600,000 - 1,000,000; Full time

Job summary

ACL Digital is seeking a Physical Design Engineer with 1-2 years of hands-on experience in block-level physical implementation for ASIC/SoC designs. You will collaborate with synthesis, STA, and physical verification teams to drive complete design flows from netlist to GDSII.

Key duties include floorplanning, placement, CTS, routing, timing closure, DRC/LVS/ERC checks, power integrity work, and developing scripts in Tcl or Python to automate the flow on Linux.

Qualifications

• 1–2 years of experience in block-level or sub-chip physical implementation.
• Experience with floorplanning, placement, CTS, routing, and timing closure.
• Familiarity with DRC/LVS/ERC checks and power integrity analysis.

Responsibilities

• Floorplanning and power planning for block-level designs.
• Placement and CTS to minimize skew and latency.
• Detailed routing and congestion resolution to optimize PPA.
• Static Timing Analysis using PrimeTime/Tempus and MMMC considerations.
• Physical verification including DRC, LVS, ERC, and Antenna checks.
• Power analysis, EM/IR drop checks, and power-aware fixes.
• Automation via Tcl, Python, or Shell scripts on Linux to streamline flows.

Skills

Floorplanning

Placement optimization

Clock Tree Synthesis

STA

Routing optimization

DRC/LVS/ERC

Power analysis

Automation scripting

Linux scripting

Tools

PrimeTime/Tempus

Python

Tcl

Shell

Job description

We are looking for a Physical Design Engineer with 1 to 2 years of hands-on experience in block-level or sub-chip physical implementation. In this role, you will work closely with senior technical leads, synthesis, STA, and physical verification teams to execute Netlist-to-GDSII design flows. You will be responsible for driving design implementation across placement, routing, clock tree synthesis, and timing closure for modern ASIC/SoC designs.

Key Responsibilities

• Floorplanning & Power Planning: Assist in block-level floorplanning, pin assignment, macro placement, and constructing low-IR drop power delivery networks (PDNs).
• Placement & CTS: Run netlist placement, optimize logic structures, and execute Clock Tree Synthesis (CTS) to achieve minimal skew and latency targets.
• Routing & Optimization: Perform detailed global/track routing, resolving congestion issues and crosstalk noise while optimizing Power, Performance, and Area (PPA).
• Static Timing Analysis (STA): Conduct STA using PrimeTime/Tempus, trace setup/hold violation paths, and implement ECO fixes across multi-mode multi-corner (MMMC) conditions.
• Physical Verification: Debug and resolve DRC, LVS, ERC, and Antenna checks to ensure clean physical layouts.
• Power Analysis: Assist senior engineers with EM/IR drop analysis (static and dynamic) and implement power-aware fixes.
• Automation: Write and maintain Tcl, Python, or Shell scripts to automate flow execution and custom data parsing in Linux environments.