Physical Design and Implementation Engineer

Google India Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Google India Pvt Ltd in Bengaluru is seeking a Mid Level Physical Design and Implementation Engineer to own ASIC RTL2GDS implementation for the CPU in the Tensor SOC. You will optimize power, performance, and area while collaborating with RTL, DFT and Foundation IP teams.

You will deploy AI-driven workflows to speed tapeouts and improve PPA, contributing to Google's CPU/GPU hardware initiatives across platforms. The role emphasizes power-aware design and high-performance silicon.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience in physical design.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for the CPU in Tensor SOC.
• Signoff convergence including STA, PDV, IR and EM.
• Manage block and subsystem physical implementation and QoR (power, timing, area).
• Optimize power, performance and area (PPA) to achieve exceptional performance and cost.
• Reduce time to market and improve PPA through deployment of AI physical design tools and workflows.

Skills

Power optimization

CPU design

RTL collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD preferred

Tools

Chip tapeouts

Job description

Physical Design and Implementation Engineer

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in physical design.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in high performance designs (CPUs , GPUs etc.).
• Experience with advanced power optimization techniques.
• Participated in 3 or more chip tape outs.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products, you'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a physical design engineer in the CPU implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing power, performance and area.

The role involves working closely with the RTL , DFT and Foundation IP teams to improve PPA.

You will deploy AI workflows to improve productivity, time to market and PPA.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware.

Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for the central processing unit (CPU) for the Tensor SOC.
• Signoff convergence including static timing analysis (STA), physical design verification (PDV), IR and Electo-Migration (EM).
• Manage block and subsystem level physical implementation and QoR (power, timing, area).
• Optimize power, performance and area (PPA) to achieve exceptional performance and cost.
• Reduce time to market and improve PPA through deployment of Artificial Intelligence (AI) physical design tools and workflows.

Experience Level

Mid Level