Physical Design and Implementation Engineer

Google; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Google is hiring a Physical Design Engineer in Bengaluru to own block or subsystem implementation for the CPU in the Tensor SOC, focusing on PPA optimization and power efficiency. You will collaborate with RTL, DFT, and IP teams to push for faster time to market with AI-driven design workflows.

The role emphasizes delivering high-performance silicon solutions for consumer products, requiring experience in physical design and chip tapeouts, with in-person interview processes common in many cases.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent practical experience.
• 4 years of experience in physical design.

Responsibilities

• Develop ASIC RTL2GDS implementation for the central processing unit (CPU) of the Tensor SOC.
• Signoff convergence including STA, PDV, IR and EM.
• Manage block and subsystem level physical implementation and QoR (power, timing, area).
• Optimize power, performance and area (PPA) to achieve exceptional performance and cost.
• Reduce time to market and improve PPA through deployment of AI physical design tools and workflows.

Skills

High performance design

Power optimization techniques

Team collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (emphasis on computer architecture)

Tools

RTL

DFT

EDA tools

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in physical design.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in high performance designs (CPUs , GPUs etc.).
• Experience with advanced power optimization techniques.
• Participated in 3 or more chip tape outs.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products, you'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a physical design engineer in the CPU implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing power, performance and area. The role involves working closely with the RTL , DFT and Foundation IP teams to improve PPA. You will deploy AI workflows to improve productivity, time to market and PPA.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for the central processing unit (CPU) for the Tensor SOC.
• Signoff convergence including static timing analysis (STA), physical design verification (PDV), IR and Electo-Migration (EM).
• Manage block and subsystem level physical implementation and QoR (power, timing, area).
• Optimize power, performance and area (PPA) to achieve exceptional performance and cost.
• Reduce time to market and improve PPA through deployment of Artificial Intelligence (AI) physical design tools and workflows.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .