Physical Design and Implementation Engineer

Google LLC; Bengaluru; On-site; INR 1,500,000 - 3,500,000; Full time

Job summary

Google LLC is seeking a Physical Design and Implementation Engineer in Bengaluru to own block or subsystem implementation of complex CPU logic, focusing on optimizing power, performance, and area. You will collaborate with RTL, DFT and IP teams to improve PPA and deploy AI workflows to boost productivity and speed to market.

The role involves in-person interactions, with in-depth knowledge of STA, PDV, IR/EM signoff processes and experience in large-scale tapeouts.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4 years of experience in physical design.
• Masters/PhD with emphasis on computer architecture preferred.
• Experience with advanced power optimization techniques.
• Participated in 3 or more chip tapeouts.

Responsibilities

• Develop ASIC RTL2GDS implementation for the CPU in the Tensor SoC.
• Signoff convergence including STA, PDV, IR/EM.
• Manage block and subsystem physical implementation and QoR (P, T, A).
• Optimize power, performance and area to achieve high PPA.
• Use AI-based physical design tools to improve productivity and time-to-market.

Skills

Electrical/CS background

Cross-functional collaboration

Problem solving

Education

Bachelor’s degree in EE/CE/CS

Master’s/PhD in EE/CE/CS (preferred)

Tools

RTL2GDS flow

STA/PDV/EM

AI PD tools

GDSII familiarity

Job description

Physical Design and Implementation Engineer

Share Physical Design and Implementation Engineer

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in physical design.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with advanced power optimization techniques.
• Participated in 3 or more chip tape outs.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products, you'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a physical design engineer in the CPU implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing power, performance and area. The role involves working closely with the RTL , DFT and Foundation IP teams to improve PPA. You will deploy AI workflows to improve productivity, time to market and PPA.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for the central processing unit (CPU) for the Tensor SOC.
• Signoff convergence including static timing analysis (STA), physical design verification (PDV), IR and Electo-Migration (EM).
• Manage block and subsystem level physical implementation and QoR (power, timing, area).
• Optimize power, performance and area (PPA) to achieve exceptional performance and cost.
• Reduce time to market and improve PPA through deployment of Artificial Intelligence (AI) physical design tools and workflows.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.