PCIe Verification Engineer

MediaTek; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

MediaTek Bengaluru seeks a Design Verification Engineer with 4+ years of hands-on experience in PCIe and/or CXL IP/subsystem verification. You will develop testbenches, run simulations, and collaborate with design teams to ensure robust RTL designs.

The ideal candidate has strong SystemVerilog/UVM skills, scripting ability (Python/Perl/Tcl), and a track record of delivering thorough verification plans and coverage metrics in fast-paced environments.

Qualifications

• 4+ years of design verification experience for PCIe/CXL IP/subsystem verification.
• Knowledge of PCIe Gen5/Gen6 is a plus.
• Proficiency in SystemVerilog, UVM and related verification tools.
• Strong RTL understanding and debugging skills.

Responsibilities

• Develop and implement verification plans for PCIe/CXL IP/subsystem.
• Create and maintain testbenches, test cases, and environments using SystemVerilog/UVM.
• Perform functional verification of RTL designs, including simulation and coverage analysis.
• Collaborate with design engineers to understand specifications and requirements.
• Identify and resolve verification issues, ensuring high-quality designs.
• Generate and analyze verification metrics to track progress.
• Participate in design/verification reviews, providing technical guidance.
• Stay updated with latest verification methodologies and apply them.
• Mentor junior verification engineers and share knowledge.

Skills

SystemVerilog

UVM

Python

Perl

Tcl

Verification methods

Problem solving

Teamwork

Education

Bachelor's/Master's in EE/CE

Job description

Position Overview

We are seeking a highly skilled and experienced Design Verification Engineer with over 4 years of experience, specifically in PCIe and/or CXL (Compute Xpress Link) IP and Subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.

Key Responsibilities

• Develop and implement comprehensive verification plans for PCIe and/or CXL IP and Subsystem.


• Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.


• Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.


• Collaborate with design engineers to understand design specifications and requirements for IP and subsystems.


• Identify and resolve design and verification issues, ensuring high-quality and robust designs.


• Generate and analyze verification metrics to track progress and ensure coverage goals are met.


• Participate in design and verification reviews, providing technical expertise and insights.


• Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.


• Mentor junior verification engineers and provide technical guidance.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.


• 4+ years of experience in design verification, with a focus on PCIe and/or CXL IP/Subsystem verification.


• Knowledge of PCIe Gen5/Gen6 protocol is a plus.


• Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.


• Strong understanding of digital design concepts, RTL coding, and simulation.


• Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.


• Excellent problem-solving skills and attention to detail.


• Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.


• Proven track record of successfully verifying complex IP blocks and subsystems.