Memory Layout Engineer

ACL Digital

Bengaluru

On-site

INR 600,000 - 1,200,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Competitive salary

Performance bonuses

Long-term growth opportunities

Job summary

A leading company in Semiconductor Manufacturing is seeking a skilled Memory Layout Engineer to design high-quality, optimized layouts for memory components. The role demands expertise in layout design, verification, and collaboration with cross-functional teams to deliver cutting-edge memory designs for AI and high-performance applications.

Qualifications

3 years of hands-on experience in custom layout design, preferably in memory design.
Deep understanding of design rules (DRC), LVS, and physical verification.
Experience with advanced FinFET and planar nodes (28nm and below).

Responsibilities

Design full-custom layouts for memory components like SRAM, ROM, CAM.
Work closely with circuit designers to translate schematics into layouts.
Run physical verification (DRC, LVS) using industry-standard tools.

Skills

CMOS layout techniques

Attention to detail

Debugging skills

Education

B.E/B.Tech or M.E/M.Tech in Electronics or Electrical Engineering

Job description

2 days ago Be among the first 25 applicants

Direct message the job poster from ACL Digital

“I don't usually stalk Profiles, but when I do I probably have a career opportunity for you.”..Lets Connect..

Job Title: Memory Layout Engineer

Experience: 3+yrs

Job Type: Full-time

Industry: Semiconductors / VLSI / Memory Design

Job Summary:

We are looking for a Memory Layout Engineer with strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will be responsible for delivering high-quality, DRC/LVS-clean layouts optimized for performance, area, and power.

Key Responsibilities:

Design full-custom layouts for memory components like SRAM, ROM, CAM, Register Files, or sense amplifiers.
Work closely with circuit designers to understand schematics and translate them into optimized layouts.
Floorplanning, transistor-level placement, routing, and matching to meet electrical and physical design constraints.
Run physical verification (DRC, LVS, ERC, antenna checks) using industry-standard tools.
Perform parasitic extraction (PEX) and assist in post-layout simulation.
Ensure layouts meet design rules for process technologies (e.g., 5nm, 7nm, 16nm, 28nm).
Implement design automation using SKILL, Python, or Tcl where applicable.
Work with cross-functional teams (circuit, verification, CAD) to meet project milestones.

Required Skills and Experience:

B.E/B.Tech or M.E/M.Tech in Electronics or Electrical Engineering.
3 years of hands-on experience in custom layout design, preferably in memory design.
Strong understanding of CMOS layout techniques, matching, shielding, and electromigration.
Experience with:
Technologies: Advanced FinFET and planar nodes (28nm and below)
Deep understanding of design rules (DRC), LVS, and physical verification sign-off flows.
Excellent attention to detail, layout quality, and debugging skills.

Preferred Qualifications:

Experience in compiler-based memory generation or memory compilers.
Exposure to high-speed or low-power memory layout optimization techniques.
Experience working with foundry design kits (PDKs) and tape-out processes.
Scripting experience in SKILL or Python for layout automation and checks.

Why Join Us?

Work on next-generation memory designs for AI, mobile, and high-performance computing chips.
Be part of a highly skilled layout team with access to leading-edge nodes and tools.
Competitive salary, performance bonuses, and long-term growth opportunities.

Interested can share Cv to Sharmila.b@acldigital.com

Seniority level