Memory Layout Design Engineer

Mirafra; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Mirafra invites skilled IC design engineers to contribute to memory architecture development. You will work on building blocks like Row Decoder, IO and Control, and apply advanced floor planning and routing strategies to meet performance and power goals.

Candidates should have strong exposure to CMOS fabrication processes, foundry interactions, and experience in compiler-level integration and verification of custom memories. Team collaboration is essential to deliver robust memory solutions.

Qualifications

• Experience in designing memory architecture components.
• Knowledge of layout concepts for placement and routing.
• Experience with EM/IR requirements and compiler memory verification.

Responsibilities

• Develop key building blocks of memory architecture such as Row Decoder, IO, and Control.
• Apply pitched layout concepts and floor planning for Placement, Power, and Global Routing.
• Ensure CMOS fabrication process knowledge and collaboration with foundries.
• Verify compiler level integration and custom memories.

Skills

Memory architecture

Row Decoder

Floor planning

Placement

Power routing

Global routing

EM/IR understanding

Compiler integration

Memory verification

CMOS process knowledge

Job description

• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories.
• Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes