Senior Memory Design Engineer

Talent Corner Hr Services; Hyderabad, Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Talent Corner Hr Services in Hyderabad is seeking an experienced memory design engineer to design and optimize SRAM, register files and ROM blocks for performance, power and area. You will collaborate with Layout, Verification and Physical Design teams to drive transistor-level design, simulation and optimization across silicon blocks.

You will mentor junior engineers and take a lead role on memory projects, with exposure to AI, HPC or Data Center SoC contexts.

Qualifications

• 515 years of experience in Memory Design with expertise in SRAM and custom circuit design.
• Hands-on experience with Cadence Virtuoso, Spectre, HSPICE, or equivalent EDA tools.
• Strong understanding of CMOS circuit design, PVT analysis, timing, power, and area optimization.
• Experience in AI, HPC, or Data Center SoC projects is preferred.
• Strong problem-solving, collaboration, and mentoring skills for senior/lead roles.

Responsibilities

• Design and develop embedded memory IPs (SRAM, Register Files, ROM).
• Perform transistor-level circuit design, simulation, and optimization.
• Optimize memory for timing, power, and area (PPA).
• Collaborate with Layout, Verification, and Physical Design teams.
• Support silicon debug and mentor junior engineers (Lead role).

Skills

Memory design

CMOS design knowledge

Mentoring/leadership

Problem solving

Tools

Cadence Virtuoso

Spectre

HSPICE

Job description

Role & responsibilities

• Design and develop embedded memory IPs (SRAM, Register Files, ROM).
• Perform transistor-level circuit design, simulation, and optimization.
• Optimize memory for timing, power, and area (PPA).
• Collaborate with Layout, Verification, and Physical Design teams.
• Support silicon debug and mentor junior engineers (Lead role).

Preferred candidate profile

• 515 years of experience in Memory Design with expertise in SRAM and custom circuit design.
• Hands-on experience with Cadence Virtuoso, Spectre, HSPICE, or equivalent EDA tools.
• Strong understanding of CMOS circuit design, PVT analysis, timing, power, and area optimization.
• Experience in AI, HPC, or Data Center SoC projects is preferred.
• Strong problem-solving, collaboration, and mentoring skills for senior/lead roles.