Manager - Design Engineering

Tessolve; Chennai District; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Tessolve is seeking a senior digital design engineer in Chennai to design and implement synthesizable RTL using Verilog and SystemVerilog. The role focuses on translating specs into micro-architecture, building high-performance, low-power blocks, and collaborating with verification and physical design teams for timing and area targets.

The candidate should have a strong background in digital logic, AMBA protocols, RTL coding standards, and experience in ASIC/SoC environments.

Qualifications

• Bachelor’s or Master’s degree in electrical or computer engineering or a related field.
• Strong expertise in Verilog/SystemVerilog and digital design fundamentals.
• Experience with AMBA protocols (AXI/AHB/APB) and RTL coding standards.

Responsibilities

• Design and develop synthesizable RTL using Verilog/SystemVerilog.
• Translate architecture specs into micro-architecture and RTL implementation.
• Develop high-performance and low-power digital design blocks.
• Collaborate with verification teams for validation and debugging.
• Perform design reviews and ensure coding quality and guidelines.
• Coordinate with physical design teams for timing and power targets.
• Debug RTL issues and support silicon bring-up.
• Work in ASIC/SoC environments with strong debugging skills.

Skills

Verilog

SystemVerilog

Digital design

RTL design

AMBA protocols

Synthesis & timing closure

Low-power design

ASIC/SoC

Debugging

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Job description

14 - 16 Years

Regular Employee - Probation

Job Description

• Design and develop synthesizable RTL using Verilog/System Verilog
• Translate architecture specifications into micro-architecture and RTL implementation
• Develop high-performance and low-power digital design blocks
• Work closely with verification teams for functional validation and debug
• Perform design reviews and ensure coding quality and design guidelines
• Collaborate with physical design teams to meet timing, power, and area requirements
• Debug RTL issues and support silicon bring-up when required
• Strong expertise in Verilog and System Verilog
• Solid understanding of digital design fundamentals and computer architecture
• Experience with AMBA protocols such as AXI, AHB, and APB
• Knowledge of synthesis, timing closure, and low-power design techniques
• Familiarity with simulation and debugging tools
• Experience working in ASIC/SoC design environments
• Strong debugging and problem-solving skills
• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design principles.

Job Snapshot

Updated Date

23-06-2026

Job ID

JOB_963

Department

Digital

Location