Principal Engineer

Cyient Limited; Telangana; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

Cyient Limited is seeking an experienced Digital Design Functional Manager in Hyderabad/Bengaluru. You will lead multiple offshore design centers, oversee RTL and SoC development, and mentor engineers while guiding architecture, execution, and delivery across semiconductor projects.

The role requires deep knowledge of digital design, Verilog/SystemVerilog, and timing closure, with strong stakeholder management and global collaboration experience. Excellent communication in English is essential.

Qualifications

• Proven experience in RTL design and SoC development.
• Strong understanding of micro-architecture planning and design trade-offs.
• Experience collaborating with verification, DFT, PD and firmware teams.

Responsibilities

• Lead and manage digital design projects across multiple ODCs and locations.
• Drive micro-architecture definition based on system requirements.
• Guide integration of industry IPs and memory controllers, high-speed interfaces.
• Estimate scope, effort and timelines for projects.
• Make technical and managerial decisions to ensure delivery.
• Collaborate with verification, physical design and software teams.
• Review design quality, code and documentation for standards.
• Identify risks and implement mitigation strategies.
• Interface with customers for requirements and status updates.

Skills

Digital design

RTL design

SoC architecture

SystemVerilog

Verilog

Timing closure

FPGA Vivado

English communication

Project leadership

Tools

Vivado

Job description

Job Title: Digital Design Functional Manager

Location: Hyderabad/Bengaluru

Department: VLSI / Digital Design

Experience: 15:18 years

Role Overview

We are seeking an experiencedDigital Design Associate lead and manage Projects activities across multiple Offshore Development Centers (ODCs), as well as internal and external semiconductor projects. The candidate will play a key role in driving architecture, execution, and delivery while mentoring engineering teams and ensuring high-quality outcomes.

Key Responsibilities

• Lead and manage digital design project across multiple ODCs and project locations.
• Drivemicro-architecture definitionbased on system requirements and ensure alignment with design goals.
• Possess strong understanding of allindustry-standard IPslike memory controllers, interconnects, peripherals, high-speed interfaces, Automotive , FuSa implementation , Low power design techniques and guide their integration ,
• Estimateproject scope, effort (man-months), and timelines.
• Make critical technical and managerial decisions to ensure successful project delivery.
• Collaborate with cross-functional teams such as verification, physical design, DFT, and software teams.
• Review design quality, code, and documentation to ensure adherence to best practices and standards.
• Identify risks proactively and implement mitigation strategies.
• Interface with customers/stakeholders for requirement gathering, status updates, and issue resolution.

Team & People Management

• Lead, mentor, and guide design engineers across experience levels.
• Onboard new hires and train freshers by developing challenging assignments and then ensuring smooth integration into projects.
• Conduct performance evaluations and provide constructive feedback.
• Allocate resources effectively across projects and ensure optimal utilization.

Required Skills & Qualifications

• Strong experience indigital design and SoC development.
• Hands-on expertise in RTL design using Verilog/SystemVerilog.
• Solid understanding ofSoC architecture and integration flows.
• Strong knowledge on industry tools
• Familiarity withindustry-standard IPsand their use in complex SoCs.
• Proven experience inmicro-architecture planning and design trade-offs.
• Ability to estimate effort, schedule, and resource requirements accurately.
• Strong decision-making and problem-solving skills.
• Excellent communication and stakeholder management abilities.
• Experience working with global teams and ODC models is highly desirable.

Preferred Qualifications

• Prior experience managing large-scale semiconductor projects.
• Exposure to end-to-end SoC lifecycle (architecture to tape-out).
• Knowledge oflow-powerdesign techniques, timing closure, and synthesis flows.
• Experience with project planning tools and methodologies.

Soft Skills

• Team-building capabilities
• Strong analytical thinking
• Ability to work under pressure and manage multiple priorities
• Proactive and ownership-driven mindset

Additional Responsibilities

• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debugCollaboration with physical design team to close the design on timing and power
• Collaboration with firmware design team to close the design system scenarios

Minimum Qualification

• 15:18 years' experience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog
• Low power (UPF) implementation. RTL sing-off.
• Experience working closely with Firmware, Verification, DFT & PD team
• Strong communication and presentation skills in English.
• Have expensein Pre-Silicon (FPGA) Validation.Engineer must have good understanding on conversion of ASIC RTL to FPGA RTL.
• Experiencein design partition on FPGA to generate multiple bit file, have good understanding on FPGA clock wizard configuration and building clock tree structure in FPGA.
• Hands-on experience in Vivado tool (Must).
• Experience in FPGA timing closure must.